Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 9/21/2023
Document Table of Contents

3.1.5. Avalon-ST Single-Device Configuration

Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements.

Figure 20. Connections for Avalon-ST x8 Single-Device Configuration
Figure 21. Connections for Avalon-ST x16 Single-Device Configuration
Figure 22. Connections for Avalon-ST x32 Single-Device Configuration

Notes for Figure:

  1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes.
  2. The synchronizers shown in all three figures can be internal if the host is an FPGA or CPLD. If the host is a microprocessor, you must use discrete synchronizers.

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