3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
- The Avalon® -ST configuration scheme requires you to monitor the flow control signal, AVST_READY. The AVST_READY signal indicates if the device can receive configuration data.
- The AVST_CLK and AVSTx8_CLK clock signals cannot pause when configuration data is not being transferred. Data is not transferred when AVST_READY and AVST_VALID are low. The AVST_CLK and AVSTx8_CLK clock signals must run continuously until CONF_DONE asserts.
Review the general Configuration Debugging Checklist in the Debugging Guide chapter before considering these debugging tips that pertain to the Avalon® -ST configuration scheme.
- Only assert AVST_VALID after the SDM asserts AVST_READY.
- Only assert AVST_VALID when the AVST_DATA is valid.
- Ensure that the AVST_CLK clock signal is continuous and free running until configuration completes. The AVST_CLK can stop after CONF_DONE asserts. The initialization state does not require the AVST_CLK signal.
- If using x8 mode, ensure that you use the dedicated SDM_IO pins for this interface (clock, data, valid and ready).
- If using x16 or x32 mode, power the I/O bank containing the x16 or x32 pins (I/O Bank 3A) at 1.8 V.
- Ensure you select the appropriate Avalon® -ST configuration scheme in your Intel® Quartus® Prime Pro Edition project.
- Ensure the MSEL pins reflect this mode on the PCB.
- Verify that the host device does not drive configuration pins before the Intel® Stratix® 10 device powers up.
- Ensure nCONFIG remains high during the configuration process.
- Verify that CONF_DONE and INIT_DONE pins correlate to the Intel® Quartus® Prime SDM I/O pins assignment and the board-level connections.
- Ensure that during the power up, no external component drives the nSTATUS signal low.
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