4.3. Gating the PLL Reset Signal
In older FPGA device families, designs frequently used the PLL lock signal to hold the custom FPGA logic in reset until the PLL locked. In newer Intel device families the lock time of PLLs can be less than the initialization time. In some cases the PLL may lock before the device completes initialization. Consequently, if you use the locked output of the PLL to control resets in the Intel® Stratix® 10 device, you should gate the PLL reset input with nINIT_DONE as shown the figure.
Another alternative if you are using PLL_Lock in your reset sequence is to gate the PLL_Lock output with the nINIT_DONE signal, (PLL_Lock && !nINIT_DONE).
Did you find the information on this page useful?