Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 9/21/2023
Document Table of Contents

4.3. Gating the PLL Reset Signal

In older FPGA device families, designs frequently used the PLL lock signal to hold the custom FPGA logic in reset until the PLL locked. In newer Intel device families the lock time of PLLs can be less than the initialization time. In some cases the PLL may lock before the device completes initialization. Consequently, if you use the locked output of the PLL to control resets in the Intel® Stratix® 10 device, you should gate the PLL reset input with nINIT_DONE as shown the figure.

Figure 62. Using nINIT_DONE to Gate the PLL_Reset Signal

Another alternative if you are using PLL_Lock in your reset sequence is to gate the PLL_Lock output with the nINIT_DONE signal, (PLL_Lock && !nINIT_DONE).

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