2.9. Dual-die Configuration on Intel® Stratix® 10 GX 10M
With the JTAG configuration scheme, each die is treated as an individual die. The configuration pins for both dies have no dependency or impact on one another. For example, the CONF_DONE and INIT_DONE pins for the first die are asserted after a successful configuration without dependency on the other die. Should the latter die fail configuration, the CONF_DONE and INIT_DONE pins for the first die are unaffected and remain high. There is no configuration sequence requirement as either die can be configured first.
Although the CONF_DONE and INIT_DONE signals are optional, Intel® recommends you assign these signals to any unused SDM pin and use these signals as an indicator to ensure that configuration is successful. These signals are important for debugging configuration.
In the Intel® Stratix® 10 GX 10M, CONF_DONE goes high before the full configuration bitstream is successfully received. During this time the device is in configuration state and waiting for data, you need to ensure the remaining 20 kB bitstream is sent before proceeding. In the event the remaining bitstream is corrupted, CONF_DONE remains high but INIT_DONE shows low, indicating you need to trigger reconfiguration.
If the Direct Interface Bus (DIB) IP is included in the design for direct communication between both dies of the Intel® Stratix® 10 GX 10M, you must ensure the setting for the DIB connection in both designs are correct and able to pass configuration.
During JTAG configuration for designs including DIB, the CONF_DONE and INIT_DONE pins of the first die are asserted once configuration is successful and the device enters user mode. If the DIB connection is incorrect, once the SDM has successfully received the entire bitstream for the second die, the SDM first asserts CONF_DONE high and soon deasserts CONF_DONE low to indicate configuration failure. Both CONF_DONE and INIT_DONE of the second die stay low until the next successful configuration. CONF_DONE and INIT_DONE for the first die continue to stay high.
The DATA UNLOCK OUTPUT is high after DIB on both dies in the same package are in user mode and ready for data transfer. When either die is reconfigured, DATA UNLOCK OUTPUT is deasserted during the operation and is asserted again once both dies are again in user mode and ready for data transfer. For more information about DIB, refer to the Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide.
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