Stratix® 10 Configuration User Guide

Download PDF
ID 683762
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Configuration User Guide 2. Stratix® 10 Configuration Details 3. Stratix® 10 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Stratix® 10 Configuration Features 7. Stratix® 10 Debugging Guide 8. Stratix® 10 Configuration User Guide Archives 9. Document Revision History for the Stratix® 10 Configuration User Guide
1. Stratix® 10 Configuration User Guide x
1.1. Stratix® 10 Configuration Overview 1.2. Stratix® 10 Configuration Architecture
1.1. Stratix® 10 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Stratix® 10 Devices
1.2. Stratix® 10 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Restricting Security Features 1.2.1.2. Updating the SDM Firmware 1.2.1.3. Specifying Boot Order for Stratix® 10 SoC Devices
2. Stratix® 10 Configuration Details x
2.1. Stratix® 10 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 2.5. Stratix® 10 Configuration Pins 2.6. Configuration Clocks 2.7. Maximum Configuration Time Estimation 2.8. Generating Compressed .sof File 2.9. Dual-die Configuration on Stratix® 10 GX 10M
2.5. Stratix® 10 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. Configuration Pins I/O Standard, Drive Strength, and IBIS Model 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Stratix® 10 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II) x
3.1.7.1. Functional Description 3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration 3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP 3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP 3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP 3.1.7.6. Supported Flash Memory Devices
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration x
3.1.7.2.1. Parallel Flash Loader II Intel® FPGA IP Parameters 3.1.7.2.2. Parallel Flash Loader II Intel® FPGA IP Signals
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP 3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address 3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration 3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins 3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
MSEL Pin Function for the AS x4 Configuration Scheme 3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
3.2.5. Skew Tolerance Guidelines x
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Disabling the Register Power-up Initialization 4.5.3. Embedded Memory Block Initial Conditions 4.5.4. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example 5.7. Debugging Guidelines for RSU Configuration
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files 5.5.1.3. Updating Decision Firmware
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Stratix® 10 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Stratix® 10 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Stratix® 10 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. SDM Debug Toolkit Overview 7.5. Configuration Pin Differences from Previous Device Families 7.6. Configuration File Format Differences 7.7. Understanding SEUs 7.8. Reading the Unique 64-Bit CHIP ID 7.9. E-Tile Transceivers May Fail To Configure 7.10. Understanding and Troubleshooting Configuration Pin Behavior 7.11. Configuration Debugger Tool
7.4. SDM Debug Toolkit Overview x
7.4.1. Using the SDM Debug Toolkit
1. Stratix® 10 Configuration User Guide
2. Stratix® 10 Configuration Details
3. Stratix® 10 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Stratix® 10 Configuration Features
7. Stratix® 10 Debugging Guide
8. Stratix® 10 Configuration User Guide Archives
9. Document Revision History for the Stratix® 10 Configuration User Guide

3.2. AS Configuration

In AS configuration schemes, the SDM block in the Stratix® 10 device controls the configuration process and interfaces. The serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot ROM. Then, the SDM loads the initial configuration firmware from AS x4 flash. After the configuration firmware loads, this firmware controls the remainder of the configuration process, including I/O configuration and FPGA core configuration. Designs including an HPS, can use the HPS to access serial flash memory after the initial configuration.

Note: The serial flash configuration device must be fully powered up at the same time or before ramping up VCCIO_SDM of the Stratix® 10 device. For more information about the power sequence, refer to the Stratix® 10 Power Management User Guide.
Important: Do not reset the quad SPI flash when used as the configuration device and data storage device with FPGA. Resetting the quad SPI flash during the FPGA configuration and reconfiguration, or in the QSPI's READ/WRITE/ERASE operations, causes undefined behavior for quad SPI flash and the FPGA. To recover from the unresponsive behavior, you must power cycle your device. To reset the quad SPI flash via the external host, you must first complete the FPGA configuration and reconfiguration, or a quad SPI operation, and only then toggle the reset. The quad SPI operation is complete when the exclusive access to the quad SPI flash is closed by issuing the QSPI_CLOSE command via the Mailbox Client Intel® FPGA IP or CLOSE command via the Serial Flash Mailbox Client Intel® FPGA IP.

The AS configuration scheme supports AS x4 (4-bit data width) mode only.

Table 31.   Stratix® 10 Configuration Data Width, Clock Rates, and Data Rates
Mode Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Active Active Serial (AS)

4

 125 MHz 500 Mbps

Fast mode - 001

Normal mode - 011
Table 32.  Required Configuration Signals for the AS Configuration Scheme
Configuration Function Pin Type Direction Powered by
nSTATUS SDM I/O Output VCCIO_SDM
nCONFIG SDM I/O Input VCCIO_SDM
MSEL[2:0] SDM I/O Input VCCIO_SDM
AS_nCSO[3:0] SDM I/O Output VCCIO_SDM
AS_DATA[3:0] SDM I/O Bidirectional VCCIO_SDM
AS_CLK SDM I/O Output VCCIO_SDM
Note: Although the CONF_DONE and INIT_DONE configuration signals are not required, Intel recommends that you use these signals. The SDM drives the CONF_DONE signal high after successfully receiving full bitstream. The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode.These signals are important when debugging configuration.

MSEL Pin Function for the AS x4 Configuration Scheme

The SDM samples the MSEL pins immediately after power-on in the SDM Start state. After the SDM samples the MSEL pins, the MSEL pins become active-low chips selects. For AS x4 designs using one flash device, AS_nCSOO asserts low when the SDM starts to communicate with the QSPI flash. The remaining chip select pins, AS_nCSO1 - AS_nCSO3 deassert high.

Note: MSEL[0] and AS_nCSOO pins share the same SDM I/O. Refer to SDM Pin Mapping for more details.

Section Content
AS Configuration Scheme Hardware Components and File Types
AS Single-Device Configuration
AS Using Multiple Serial Flash Devices
AS Configuration Timing Parameters
Skew Tolerance Guidelines
Programming Serial Flash Devices
Serial Flash Memory Layout
AS_CLK
Active Serial Configuration Software Settings
Quartus Prime Programming Steps
Debugging Guidelines for the AS Configuration Scheme

Related Information
Level Two Title