ID 683619
Date 9/24/2018
Public

## 1.7.2. Specifying Board Trace Model Settings

The SSN Analyzer uses circuit models to determine voltage noise during SSN analysis. The circuit topology is incomplete without board trace information and PCB layer information.

To accurately compute the SSN in your FPGA device, you must describe the board trace and PCB layer parameters in your design. If you do not specify some or all the board trace parameters and PCB layer information, the SSN Analyzer uses default parameters, which set the SSN confidence level to low.

The SSN Analyzer requires board trace models such as termination resistors, pin loads (capacitance), and transmission line parameters. You can define the board circuit models—or board trace models, in the Intel® Quartus® Prime software.

You can define an overall board trace model for each I/O standard in your design. This overall model is the default model for all pins that use a particular I/O standard. After configuring the overall board trace model, you can customize the model for specific pins.

Intel® Quartus® Prime software uses the parameters you specify for the board trace model during advanced I/O timing analysis with the Timing Analyzer.

If you already specified the board trace models as part of your advanced I/O timing assignments, Intel® Quartus® Prime software uses the same parameters during SSN analysis.

All the assignments for board trace models you specify are saved to the .qsf file. You can also use Tcl commands to create board trace model assignments.

### Tcl Commands for Specifying Board Trace Models

set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH "3.041E-7" -to e[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.1391 -to e[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH "1.463E-10" -to e[0]

The best way to calculate transmission line parameters is to use a two-dimensional solver to estimate the inductance per inch and capacitance per inch for the transmission line. You can obtain the termination resistor topology information from the PCB schematics. The near-end and far-end pin load (capacitance) values can be obtained from the PCB schematic and other device data sheets. For example, if you know that an FPGA pin is driving a DIMM, you can obtain the far-end loading information in the data sheet for your target device.