Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

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ID 683619
Date 9/24/2018
Public
Document Table of Contents

1.7.1. Optimizing Pin Placements for Signal Integrity

The SSN Optimization logic option tells the Fitter to adjust the pin placement to reduce the SSN in the design.

The SSN Optimization logic option has three possible values: Off, Normal compilation, and Extra Effort.

If you use the SSN Optimization logic option, avoid creating location assignments for your pins. Instead, let the Fitter place the pins during compilation to meet the timing performance of your design.

To display the Fitter-placed pins use the Show Fitter Placements feature in the Pin Planner. To accept these suggested pin locations, you must back-annotate your pin assignments.

Note: Setting the SSN Optimization option to Extra effort may impact your design fMAX.
Figure 8. SSN Analysis Results Before and After Using the SSN Optimization Logic OptionThe image shows the pin placement before and after turning on the SSN Optimization logic option.

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