Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

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ID 683619
Date 9/24/2018
Public
Document Table of Contents

1.7.4. Specifying Signal Breakout Layers

Each user I/O pin in your FPGA device can break out at different layers on your PCB. In the Pin Planner, you can specify on which layers the I/O pins in your design break out.

The breakout layer information is used only during SSN analysis and is not used in other processes run by the Intel® Quartus® Prime software. To assign a pin to PCB layer, follow these steps:

  1. On the Assignments menu, click Pin Planner.
  2. If necessary, perform Analysis & Elaboration, Analysis & Synthesis, or fully compile the design to populate the Pin Planner with the node names in the design.
  3. Right-click anywhere in the All Pins or Groups list, and then click Customize Columns.
  4. Select the PCB layer column and move it from the Available columns list to the Show these columns in this order list.
  5. Click OK.
  6. In the PCB layer column, specify the PCB layer to which you want to connect the signal.
  7. On the File menu, click Save Project to save the changes.
    Note: When you create PCB breakout layer assignments in the Pin Planner, you can assign the pin to any layer, even if you did not yet define the PCB layer.

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