Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

ID 683619
Date 9/24/2018
Document Table of Contents

2.4.2. Creating Accurate IBIS Models

There are two methods to obtain Intel device IBIS files for your board-level signal integrity simulations. You can download generic IBIS models from the Altera website. You can also use the IBIS writer in the Intel® Quartus® Prime software to create design-specific models.

The IBIS file generated by the Intel® Quartus® Prime software contains models of both input and output termination, and is supported for IBIS model versions of 4.2 and later. Arria® V , Cyclone® V , and Stratix® V device families allow the use of bidirectional I/O with dynamic on-chip termination (OCT).

Dynamic OCT is used where a signal uses a series on-chip termination during output operation and a parallel on-chip termination during input operation. Typically this is used in Altera External Memory Interface IP.

The Intel® Quartus® Prime IBIS dynamic OCT IBIS model names end in g50c_r50c. For example : sstl15i_ctnio_g50c_r50c.

In the simulation tool, the IBIS model is attached to a buffer.
  • When the buffer is assigned as an output, use the series termination r50c.

  • When the buffer is assigned as an input, use the parallel termination g50c.

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