Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

ID 683619
Date 9/24/2018
Document Table of Contents

2.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software

You must integrate IBIS models downloaded from the Altera website or created with the Intel® Quartus® Prime IBIS Writer into board design simulations to accurately model timing and signal integrity.

The HyperLynx* software from Mentor Graphics* is one of the most popular tools for design simulation. The HyperLynx* software makes it easy to integrate IBIS models into simulations.

The HyperLynx* software is a PCB analysis and simulation tool for high-speed designs, consisting of two products, LineSim and BoardSim.

LineSim is an early simulation tool. Before any board routing takes place, you use LineSim to simulate “what if” scenarios that assist in creating routing rules and defining board parameters.

BoardSim is a post-layout tool that you use to analyze existing board routing. You select one or more nets from a board layout file and BoardSim simulates those nets in a manner similar to LineSim. With board and routing parameters, and surrounding signal routing known, highly accurate simulations of the final fabricated PCB are possible.

This section focuses on LineSim. Because the process of creating and running simulations is very similar for both LineSim and BoardSim, the details of IBIS model use in LineSim applies to simulations in BoardSim.

You configure simulations in LineSim using a schematic GUI to create connections and topologies between I/O buffers, route trace segments, and termination components. LineSim provides two methods for creating routing schematics: cell-based and free-form. Cell-based schematics are based on fixed cells consisting of typical placements of buffers, trace impedances, and components. Parts of the grid-based cells are filled with the desired objects to create the topology. A topology in a cell-based schematic is limited by the available connections within and between the cells.

A more robust and expandable way to create a circuit schematic for simulation is to use the free-form schematic format in LineSim. The free-form schematic format makes it easy to place parts into any configuration and edit them as required. This section describes the use of IBIS models with free-form schematics, but the process is nearly identical for cell-based schematics.

Figure 13. HyperLynx LineSim Free-Form Schematic Editor

When you use HyperLynx* software to perform simulations, you typically perform the following steps:

  1. Create a new LineSim free-form schematic document and set up the board stackup for your PCB using the Stackup Editor. In this editor, specify board layer properties including layer thickness, dielectric constant, and trace width.
  2. Create a circuit schematic for the net you want to simulate. The schematic represents all the parts of the routed net including source and destination I/O buffers, termination components, transmission line segments, and representations of impedance discontinuities such as vias or connectors.
  3. Assign IBIS models to the source and destination I/O buffers to represent their behavior during operation.
  4. Attach probes from the digital oscilloscope that is built in to LineSim to points in the circuit that you want to monitor during simulation. Typically, at least one probe is attached to the pin of a destination I/O buffer. For differential signals, you can attach a differential probe to both the positive and negative pins at the destination.
  5. Configure and run the simulation. You can simulate a rising or falling edge and test the circuit under different drive strength conditions.
  6. Interpret the results and make adjustments. Based on the waveforms captured in the digital oscilloscope, you can adjust anything in the circuit schematic to correct any signal integrity issues, such as overshoot or ringing. If necessary, you can make I/O assignment changes in the Intel® Quartus® Prime software, regenerate the IBIS file with the IBIS Writer, and apply the updated IBIS model to the buffers in your HyperLynx* software schematic.
  7. Repeat the simulations and circuit adjustments until you are satisfied with the results.
  8. When the operation of the net meets your design requirements, implement changes to your I/O assignments in the Intel® Quartus® Prime software and optionally adjust your board routing constraints, component values, and placement to match the simulation.
For more information about HyperLynx* software, including schematic creation, simulation setup, model usage, product support, licensing, and training, refer to the Mentor Graphics* webpage.

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