1. Simultaneous Switching Noise (SSN) Analysis and Optimizations 2. Signal Integrity Analysis with Third-Party Tools 3. Mentor Graphics* PCB Design Tools Support 4. Cadence PCB Design Tools Support 5. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software A. Intel® Quartus® Prime Standard Edition User Guides
1.1. Simultaneous Switching Noise (SSN) Analysis and Optimizations 1.2. Definitions 1.3. Understanding SSN 1.4. SSN Estimation Tools 1.5. SSN Analysis Overview 1.6. Design Factors Affecting SSN Results 1.7. Optimizing Your Design for SSN Analysis 1.8. Performing SSN Analysis and Viewing Results 1.9. Decreasing Processing Time for SSN Analysis 1.10. Scripting Support 1.11. Document Revision History
1.7.1. Optimizing Pin Placements for Signal Integrity 1.7.2. Specifying Board Trace Model Settings 1.7.3. Defining PCB Layers and PCB Layer Thickness 1.7.4. Specifying Signal Breakout Layers 1.7.5. Creating I/O Assignments 1.7.6. Decreasing Pessimism in SSN Analysis 1.7.7. Excluding Pins as Aggressor Signals
2.4.1. Elements of an IBIS Model 2.4.2. Creating Accurate IBIS Models 2.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software 2.4.4. Configuring LineSim to Use Intel IBIS Models 2.4.5. Integrating Intel IBIS Models into LineSim Simulations 2.4.6. Running and Interpreting LineSim Simulations
2.5.1. Supported Devices and Signaling 2.5.2. Accessing HSPICE Simulation Kits 2.5.3. The Double Counting Problem in HSPICE Simulations 2.5.4. HSPICE Writer Tool Flow 2.5.5. Running an HSPICE Simulation 2.5.6. Interpreting the Results of an Output Simulation 2.5.7. Interpreting the Results of an Input Simulation 2.5.8. Viewing and Interpreting Tabular Simulation Results 2.5.9. Viewing Graphical Simulation Results 2.5.10. Making Design Adjustments Based on HSPICE Simulations 2.5.11. Sample Input for I/O HSPICE Simulation Deck 2.5.12. Sample Output for I/O HSPICE Simulation Deck 2.5.13. Advanced Topics
188.8.131.52. Applying I/O Assignments 184.108.40.206. Enabling HSPICE Writer 220.127.116.11. Enabling HSPICE Writer Using Assignments 18.104.22.168. Naming Conventions for HSPICE Files 22.214.171.124. Invoking HSPICE Writer 126.96.36.199. Invoking HSPICE Writer from the Command Line 188.8.131.52. Customizing Automatically Generated HSPICE Decks
184.108.40.206. Header Comment 220.127.116.11. Simulation Conditions 18.104.22.168. Simulation Options 22.214.171.124. Constant Definition 126.96.36.199. I/O Buffer Netlist 188.8.131.52. Drive Strength 184.108.40.206. Slew Rate and Delay Chain 220.127.116.11. I/O Buffer Instantiation 18.104.22.168. Board and Trace Termination 22.214.171.124. Double-Counting Compensation Circuitry 126.96.36.199. Simulation Analysis
3.2.1. Generating Pin Assignment Files 3.2.2. I/O Designer Settings 3.2.3. Transferring I/O Assignments 3.2.4. Updating I/O Designer with Intel® Quartus® Prime Pin Assignments 3.2.5. Updating Intel® Quartus® Prime with I/O Designer Pin Assignments 3.2.6. Generating Schematic Symbols in I/O Designer 3.2.7. Exporting Schematic Symbols to DxDesigner
4.1. Cadence PCB Design Tools Support 4.2. Product Comparison 4.3. FPGA-to-PCB Design Flow 4.4. Setting Up the Intel® Quartus® Prime Software 4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software 4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software 4.7. Document Revision History
5.1. Reviewing Intel® Quartus® Prime Software Settings 5.2. Reviewing Device Pin-Out Information in the Fitter Report 5.3. Reviewing Compilation Error and Warning Messages 5.4. Using Additional Intel® Quartus® Prime Software Features 5.5. Using Additional Intel® Quartus® Prime Software Tools 5.6. Document Revision History
3.1. FPGA-to-PCB Design Flow
You can create a design flow integrating an Intel FPGA design from the Intel® Quartus® Prime software, and a circuit schematic in the DxDesigner software.
Figure 28. Design Flow with and Without the I/O Designer Software
Note: The Intel® Quartus® Prime software generates the .fx in the output directory you specify in the Board-Level page of the Settings dialog box. However, the Intel® Quartus® Prime software and the I/O Designer software can import pin assignments from an .fx located in any directory. Use a backup .fx to prevent overwriting existing assignments or importing invalid assignments.
To integrate the I/O Designer into your design flow, follow these steps:
- In the Intel® Quartus® Prime software, click Assignments > Settings > EDA Tool Settings > Board-Level to specify settings for .fx symbol file generation.
- Compile your design to generate the .fx and Pin-Out File (.pin) in the Intel® Quartus® Prime project directory.
- Create a board design with the DxDesigner software and the I/O Designer software by performing the following steps:
- Create a new I/O Designer database based on the .fx and the .pin files.
- In the I/O Designer software, make adjustments to signal and pin assignments.
- Regenerate the .fx in the I/O Designer software to export the I/O Designer software changes to the Intel® Quartus® Prime software.
- Generate a single or fractured symbol for use in the DxDesigner software.
- Add the symbol to the sym directory of a DxDesigner project, or specify a new DxDesigner project with the new symbol.
- Instantiate the symbol in your DxDesigner schematic and export the design to the board layout tool.
- Back-annotate pin changes created in the board layout tool to the DxDesigner software and back to the I/O Designer software and the Intel® Quartus® Prime software.
- Create a board design with the DxDesigner software without the I/O Designer software by performing the following steps:
- Create a new DxBoardLink symbol with the Symbol wizard and reference the .pin from the Intel® Quartus® Prime software in an existing DxDesigner project.
- Instantiate the symbol in your DxDesigner schematic and export the design to a board layout tool.
Note: You can update these symbols with design changes with or without the I/O Designer software. If you use the Mentor Graphics* I/O Designer software and you change symbols with the DxDesigner software, you must reimport the symbols into I/O Designer to avoid overwriting your symbol changes.
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