Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

ID 683619
Date 9/24/2018
Document Table of Contents Simulation Analysis

The simulation analysis block of the simulation file is configured to measure the propagation delay from the source to the FPGA pin. Both the source and end point of the delay are referenced against the 50% VCCN crossing point of the waveform.

Simulation Analysis Block

* Simulation Analysis Setup

* Print out the voltage waveform at both the source and the pin
.print tran v(source)  v(pin)
.tran 0.020ns 17ns

* Measure the propagation delay from the source pin to the pin
* referenced against the 50% voltage threshold crossing point

.measure TRAN tpd_rise TRIG v(source) val=’vcn*0.5’ rise=1
+ TARG v(pin) val =’vcn*0.5’ rise=1
.measure TRAN tpd_fall TRIG v(source) val=’vcn*0.5’ fall=1
+ TARG v(pin) val =’vcn*0.5’ fall=1

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