Intel® Quartus® Prime Standard Edition User Guide: PCB Design Tools

ID 683619
Date 9/24/2018
Public
Document Table of Contents

4.6.3. Generating Schematic Symbol

You can now create a new symbol to represent your FPGA design in your schematic.

To generate a schematic symbol, follow these steps:

  1. Start the Cadence Allegro Design Entry CIS software.
  2. On the Tools menu, click Generate Part. The Generate Part dialog box appears.
  3. To specify the .pin from your Intel® Quartus® Prime design, in the Netlist/source file type field, click Browse.
  4. In the Netlist/source file type list, select Altera Pin File
  5. Type the new part name.
  6. Specify the Destination part library for the symbol. Failing to select an existing library for the part creates a new library with a default name that matches the name of your Cadence Allegro Design Entry CIS project.
  7. To create a new symbol for this design, select Create new part. If you updated your .pin in the Intel® Quartus® Prime software and want to transfer any assignment changes to an existing symbol, select Update pins on existing part in library.
  8. Select any other desired options and set Implementation type to <none>. The symbol is for a primitive library part based only on the .pin and does not require special implementation. Click OK.
  9. Review the Undo warning and click Yes to complete the symbol generation.

    You can locate the generated symbol in the selected library or in a new library found in the Outputs folder of the design in the Project Manager window. Double-click the name of the new symbol to see its graphical representation and edit it manually using the tools available in the Cadence Allegro Design Entry CIS software.

    Note: For more information about creating and editing symbols in the Cadence Allegro Design Entry CIS software, refer to the Help in the software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message