22.214.171.124. Customizing Automatically Generated HSPICE Decks
A default board description is included, and a default simulation is set up to measure rise and fall delays for both input and output simulations, which compensates for the double counting problem. However, Intel recommends that you customize the board description to more accurately represent your routing and termination scheme.
The sample board trace loading in the generated HSPICE model files must be replaced by your actual trace model before you can run a correct simulation. To do this, open the generated HSPICE model files for all pins you want to simulate and locate the following section.
Sample Board Trace Section
* I/O Board Trace and Termination Description * - Replace this with your board trace and termination description
You must replace the example load with a load that matches the design of your PCB board. This includes a trace model, termination resistors, and, for output simulations, a receiver model. The spice circuit node that represents the pin of the FPGA package is called pin. The node that represents the far pin of the external device is called load-in (for output SPICE decks) and source-in (for input SPICE decks).
For an input simulation, you must also modify the stimulus portion of the spice file. The section of the file that must be modified is indicated in the following comment block.
Sample Source Stimulus Section
* Sample source stimulus placeholder * - Replace this with your I/O driver model
Replace the sample stimulus model with a model for the device that drives the FPGA.
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