Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset


One or more of the PLLs in the hard processor system (HPS) of Cyclone V SoC devices can take a long time to lock after power-on reset or cold reset. This occurs when the clock select (CSEL) pins are set to 01, 10, or 11. Some peripherals clocked by the HPS PLLs may fail to operate properly. While this failure is rare, typical symptoms include:

  • The HPS hangs during the Boot ROM stage and is unable to proceed to the Preloader stage.
  • An intermittent SDRAM calibration error in the Preloader.


These issues can be resolved by implementing the following changes:

  1. Connect the CSEL pins [1:0] to pull down resistors (4.7 kΩ to 10 kΩ) on the board to force the CSEL input to be 0.
  2. Download and install the appropriate SoCEDS patch for software version 13.1 or 14.0. Then, recompile the Preloader code.

To download and install the required SoCEDS patch for SoCEDS version 13.1 and 14.0, refer to KDB solution rd06202014. Software in the patch is integrated into SoCEDS version 14.0.1.

Selecting CSEL=00 causes the Boot ROM to bypass the PLLs on cold reset, instead using the external clock input (osc_1_clk) for the peripheral interfaces. Because the external clock is already stable, using it ensures the Preloader code loads properly from external Flash.

The software patch adds code to the Preloader, which locks the PLLs quickly, which in turn resolves the intermittent SDRAM calibration issue. It also loads a piece of code into the on-chip RAM to handle a warm reset. Clocks are handled differently depending on whether the reset is warm or cold.

Bypassing the PLLs after cold reset increases the boot time slightly because the external clock is slower than the Flash interface clock generated from the HPS peripheral PLL. Intel reserves the upper 4 KB of on-chip RAM for the warm boot code.

Note: Do not overwrite the content of the upper 4 KB of the address range in the on-chip RAM. If you need a smaller memory footprint for the code, file a service request using Intel® Premier Support.

The on-chip memory restriction can be eliminated entirely if the SoC warm and cold reset pins are tied together, or if the HPS boots from FPGA memory.


Affects: All Cyclone® V SX, ST, and SE devices

Table 3.  Device and Revision FixedThis table identifies the fixed silicon by die revision for each device.
Device Revision without Fix Revision with Fix
5CSEA2 Rev B Rev C
5CSEA4 Rev B Rev C
5CSEA5 Rev C Rev D
5CSEA6 Rev C Rev D
5CSXC2 Rev B Rev C
5CSXC4 Rev B Rev C
5CSXC5 Rev C Rev D
5CSXC6 Rev C Rev D
5CSTD5 Rev C Rev D
5CSTD6 Rev C Rev D
Figure 2.  Intel Date Code Marking FormatThis figure shows the silicon revision as identified by the fourth letter of the lot ID.