Cyclone® V SX, ST and SE SoC Device Errata

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ID 683618
Date 9/25/2015
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Document Table of Contents x
1. Cyclone® V SX, ST and SE SoC Device Errata
1. Cyclone® V SX, ST and SE SoC Device Errata x
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices 1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata 1.3. Revision History for Cyclone® V SX, ST, and SE SoC Device Errata
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices x
1.1.1. Hard Processor System (HPS) 1.1.2. FPGA
1.1.1. Hard Processor System (HPS) x
1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric 1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code 1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset 1.1.1.4. HPS TAP Controller Is Reset By Cold Reset 1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
1.1.2. FPGA x
1.1.2.1. External Memory Interface (EMIF) Maximum Frequency Specification Updage 1.1.2.2. Fractional PLL Phase Alignment Error 1.1.2.3. Power Connection Recommendation for Cyclone® V SoC ES Devices 1.1.2.4. Configuration via Protocol (CvP) 1.1.2.5. Usermode High Icc 1.1.2.6. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.1.2.7. JTAG Programming Operation Issue
1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata x
1.2.1. Arm* Cortex* -A9 MPU 1.2.2. Arm* L2 Cache Controller 1.2.3. Arm* CoreSight PTM
1.2.1. Arm* Cortex* -A9 MPU x
1.2.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 1.2.1.2. 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock 1.2.1.3. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock 1.2.1.4. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock 1.2.1.5. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 1.2.1.6. 740657: Global Timer Can Send Two Interrupts for the Same Event 1.2.1.7. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 1.2.1.8. 754322: Faulty MMU Translations Following ASID Switch 1.2.1.9. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault 1.2.1.11. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 1.2.1.12. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 1.2.1.13. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 1.2.1.14. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 1.2.1.15. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 1.2.1.16. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 1.2.1.17. 751471: DBGPCSR Format Is Incorrect 1.2.1.18. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 1.2.1.19. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 1.2.1.20. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 1.2.1.21. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 1.2.1.22. 761321: MRC and MCR Are Not Counted in Event 0x68 1.2.1.23. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 1.2.1.24. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value 1.2.1.25. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock Description Impact Workaround Category 1.2.1.27. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back 1.2.1.28. 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region
1.2.2. Arm* L2 Cache Controller x
1.2.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 1.2.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 1.2.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
1.2.3. Arm* CoreSight PTM x
1.2.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 1.2.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. Cyclone® V SX, ST and SE SoC Device Errata

1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock

Description

On the Cortex* -A9, when a cacheable read receives an external abort, the aborted line is allocated as invalid in the data cache, and any allocation in the data cache clears the internal exclusive monitor.

Therefore, if a program executes a LDREX/STREX loop that continues to receive an abort answer in the middle of the LDREX/STREX sequence, then the LDREX/STREX sequence never succeeds, leading to a possible processor livelock.

As an example, the following code sequence might exhibit this erratum: 

loop LDREX
...
DSB
STREX
CMP
BNE loop
...
LDR (into aborting region)

The LDREX/STREX does not succeed on the first pass of the loop, the BNE is mispredicted, and the LDR afterward is speculatively executed.

Therefore the processor keeps on executing:

LDR to aborting region (this speculative LDR now appears “before” the LDREX & DSB)
LDREX
DSB
STREX

The LDR misses in L1 and never gets allocated as valid because it is aborting.

The LDREX executes and sets the exclusive monitor.

The DSB executes. It waits for the LDR to complete, which aborts, causing an allocation (as invalid) in the data cache, clearing the exclusive monitor. The STREX executes, but the exclusive monitor is now cleared, so the STREX fails. The BNE might be mispredicted again, therefore the LDR is speculatively executed again, and the code loops back on the same failing LDREX/STREX sequence.

This erratum happens in systems that might generate external aborts in answer to cacheable memory requests.

Impact

If the program reaches a stable state where the internal exclusive monitor continues to be cleared in the middle of the LDREX/STREX sequence, then the processor might encounter a livelock situation.

In practice, this scenario is very unlikely to happen because several conditions might prevent it:

  • Normal LDREX/STREX code sequences do not contain any DSB, so it is very unlikely that the system would return the abort answer precisely in the middle of the LDREX/STREX sequence on each iteration.
  • Some external irritants (for example, interrupts) might happen and cause timing changes that might exit the processor from its livelock situation.
  • Branch prediction is usually enabled, so the final branch in the loop is usually predicted correctly after a few iterations of the loop, preventing the speculative LDR from being issued, so that the next iteration of the LDREX/STREX sequence succeeds.

Workaround

For this erratum, either of the following workarounds fixes the problem:

  • Turn on the branch prediction.
  • Remove the DSB in the middle of the LDREX/STREX sequence. If a DSB is required, Arm* recommends that you place it before the LDREX/STREX sequence, and implement the LDREX/STREX sequence as recommended by the Arm* architecture.

Category

Category 3

Level Two Title