Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock


Under very rare circumstances, full cache line writes from the two processors on cache lines in hazard with other request may cause arbitration issues in the SCU, leading to processor deadlock.

This erratum only affects dual-core devices. To trigger this erratum, the two processors must be performing full cache line writes to cache lines which are in coherent memory regions and are in hazard with other access requests in the Snoop Control Unit (SCU). The hazard in the SCU happens when the Accelerator Coherency Port (ACP) is performing a read or a write of the same cache line.

Under certain rare timing circumstances, the requests might create a loop of dependencies causing a processor deadlock.


This erratum can cause system deadlock. It is important to note that any scenario leading to this deadlock situation is uncommon. It requires both processors writing full cache lines to a coherent memory region, without taking any semaphore, with the ACP assessing the same lines at the same time, meaning that these latter accesses are not deterministic. This condition, combined with the extremely rare microarchitectural timing conditions under which the defect can happen, explains why this erratum is not expected to cause any significant malfunction in real systems.


This erratum can be worked around by setting bit[21] of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1.

This bit can be written in secure state only, with the following read/modify/write code sequence:
MCR p15, 0, rt, c15, c0, 1
ORR rt, rt #0x200000
MCR p15, 0, rt, c15, c0, 1
When this bit is set, the "direct eviction" optimization in the bus interface unit is disabled, which means this erratum cannot occur.

Setting this bit might prevent the Cortex-A9 from utilizing the full bandwidth when performing intensive full cache line writes and therefore a slight performance drop might be visible.

In addition, this erratum cannot occur if at least one of the following bits in the diagnostic control register is set to 1:

  • bit[23]: Disable read-allocate mode
  • bit[22]: Disable write-allocate wait mode


Category 2