- 188.8.131.52. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
- 184.108.40.206. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
- 220.127.116.11. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
- 18.104.22.168. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
- 22.214.171.124. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
- 126.96.36.199. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
- 188.8.131.52. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
- 184.108.40.206. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
- 220.127.116.11. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
- 18.104.22.168. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
- 22.214.171.124. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
- 126.96.36.199. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
- 188.8.131.52. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
- 184.108.40.206. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
220.127.116.11. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
Under very rare timing circumstances, data corruption might occur on a dirty cache line that is evicted from the L1 data cache due to another cache line being entirely written.
The erratum requires the following conditions:
- The CPU contains a dirty line in its data cache.
- The CPU performs at least four full cache line writes, one of which is causing the eviction of the dirty line.
- The other CPU, or the ACP, is performing a read or write operation on the dirty line.
The issue requires very rare timing conditions to reach the point of failure. These timing conditions depend on the CPU micro-architecture, and are not controllable in software:
- The CPU must be in a transitional mode that might be triggered by the detection of the first two full cache line writes.
- The evicted line must remain stalled in the eviction buffer, which is likely to be caused by congested write traffic.
- The other coherent agent, either the other CPU or the ACP, must perform its coherency request on the evicted line while it is in the eviction buffer.
This erratum might lead to data corruption.
A workaround for this erratum is provided by setting bit of the undocumented Diagnostic Control Register to 1. This register is encoded as CP15 c15 0 c0 1. The bit can be written in secure state only, with the following read-modify-write code sequence:
MRC p15,0,rt,c15,c0,1 ORR rt,rt,#0x00400000 MCR p15,0,rt,c15,c0,1
When this bit is set, the processor is unable to switch into read-allocate (streaming) mode, which means this erratum cannot occur.
Setting this bit could possibly result in a visible drop in performance for routines that perform intensive memory accesses, such as memset() or memcpy(). However, the workaround is not expected to create any significant performance degradation in most standard applications.
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