Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock


Under certain timing circumstances, a processor might deadlock when the execution of a write to a strongly-ordered memory region is followed by the speculative execution of a Load-Exclusive (LDREX) or a Store-Exclusive (STREX) instruction that is not speculated correctly. This incorrect speculation can be due to either the LDREX or STREX instruction being conditional and failing its condition code check or to the LDREX or STREX instruction being speculatively executed in the shadow of a mispredicted branch.

This erratum requires the following conditions:
  • The processor executes a write instruction to a strongly-ordered memory region.
  • The process speculatively executes a Load-Exclusive or Store-Exclusive instruction that is either:
    • A conditional instruction
    • An instruction in the shadow of a conditional branch.
  • The Load-Exclusive or Store-Exclusive instruction is canceled because the speculation was incorrect, due to one of the following conditions:
    • The conditional Load-Exclusive or Store-Exclusive instruction failed its condition-code check.
    • The conditional branch was mispredicted so that all subsequent instructions speculatively executed must be flushed, including the Load-Exclusive or Store-Exclusive.

This erratum also requires additional timing conditions to be met. These are specific to each platform, and are not controllable by software. One timing condition that can cause this erratum is when the response to the strongly-ordered write from the external memory system must be received at the same time as the mispeculation is identified in the processor.


This erratum can cause a processor deadlock.


The recommended workaround is to place a DMB instruction before each Load-Exclusive/Store-Exclusive loop sequence, to ensure that no pending write request can interfere with the executing of the LDREX or STREX instructions. The implementation of this workaround can be restricted to code regions which have access to strongly-ordered memory.


Category 2