Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region


A write to a strongly ordered memory region, followed by the execution of an LDREX instruction can cause the “STREX-passed” event to be signaled even if no STREX instruction is executed.

As a result, the event 0x63 count might be faulty, reporting too many “STREX-passed” events. This erratum also affects the associated PMUEVENT[27] signal. This signal will report the same spurious events.

This erratum requires the following conditions:

  1. The processor executes a write instruction to a strongly-ordered memory region.
  2. The processor executes an LDREX instruction.
  3. No DSB instruction is executed and there is no exception call or exception return between the write and the STREX instructions.

Under these conditions, if the write instruction to the strongly ordered memory region receives its acknowledge (BRESP response on AXI) while the LDREX is being executed, this erratum can happen.


This erratum leads to a faulty count of event 0x63 or incorrect signaling of PMUEVENT[27].


The workaround for this erratum is to insert a DMB or DSB instruction between the write to a strongly ordered memory region and the LDREX instruction.


Category 3