- 126.96.36.199. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
- 188.8.131.52. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
- 184.108.40.206. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
- 220.127.116.11. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
- 18.104.22.168. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
- 22.214.171.124. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
- 126.96.36.199. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
- 188.8.131.52. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
- 184.108.40.206. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
- 220.127.116.11. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
- 18.104.22.168. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
- 22.214.171.124. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
- 126.96.36.199. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
- 188.8.131.52. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
184.108.40.206. 761321: MRC and MCR Are Not Counted in Event 0x68
Event 0x68 counts the total number of instructions passing through the register rename pipeline stage. The event is also reported externally on PMUEVENT[9:8]. However, with this erratum, the MRC and MCR instructions are not counted in this event or reported externally on PMUEVENT[9:8]..
The implication of this erratum is that the values of event 0x68 and PMUEVENT[9:8] are imprecise, omitting the number of MCR and MRC instructions. The inaccuracy of the total count depends on the rate of MRC and MCR instructions in the code.
No workaround is possible to achieve the required functionality of counting precisely how many instructions are passing through the register rename pipeline stage when the code contains some MRC or MCR instructions.
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