Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents JTAG Programming Operation Issue


JTAG configuration of 28-nm devices does not operate correctly when you initiate a PAUSE_DR instruction during configuration. In this scenario, JTAG configuration fails when you pause configuration in the middle of the bit stream by entering into the PAUSE-DR state and continuing to clock the TCK input. The failure is indicated by CONF_DONE staying low after all of the data has been clocked into the FPGA while nSTATUS remains high.

The PAUSE-DR feature works correctly with normal IEEE 1149.1 JTAG test operations


If you must pause in the middle of the bit stream during JTAG configuration, halt the TCK and do not enter the PAUSE-DR state. Restart the TCK when you resume the configuration.


Affects: Cyclone® V SX, ST, and SE devices

Status: No planned fix