Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock


Under certain micro-architectural circumstances, a data cache maintenance operation which aborts, followed by an ISB with no DSB occurring between these events, might light lead to processor deadlock.

This erratum requires the following conditions:
  1. Some of the write operations are being handled by the processor and take a long time to complete. The typical situation is when the write operation, such as STR, STM, has missed in the L1 data cache.
  2. No memory barrier (DMB or DSB) is inserted between the write operation and the data cache maintenance operation mentioned in condition 3.
  3. A data cache maintenance operation is performed, which aborts because of its MMU settings.
  4. No memory barrier (DMB or DSB) is inserted between the data cache maintenance operation in condition 3 and the ISB in condition 5. Any other kind of code can be executed here, starting with the abort exception handler following the aborted cache maintenance operation.
  5. An DMB ISB instruction is being executed by the processor.
  6. No memory barrier ( or DSB) is inserted between the ISB in condition 5 and the read or write operation in condition 7.
  7. A read or write operation is executed.

With the above conditions, an internal "Data Side drain request" signal might remain sticky causing the ISB to wait for the data side to empty, which never happens because the last read or write operation waits for the ISB to complete.


This erratum can lead to processor deadlock.


A simple workaround for this erratum is to add a DSB at the beginning of the abort exception handler.


Category 2