Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D


The ISB is implemented as a branch in the Cortex* -A9 microarchitecture. Because ISB acts as a branch, events 0x0C (software change of PC) and 0x0D (immediate branch) are asserted when an ISB occurs, which is not compliant with the Arm* architecture.


The count of events 0x0C and 0x0D are not completely precise when using the Performance Monitor counters, because the ISB is counted together with the real software changes to the PC (for 0x0C) and immediate branches (0x0D).

This erratum also causes the corresponding PMUEVENT bits to toggle in case an ISB executes.
  • PMUEVENT[13] relates to event 0x0C.
  • PMUEVENT[14] relates to event 0x0D.


You can count ISB instructions alone with event 0x90.

You can subtract this ISB count from the results you obtained in events 0x0C and 0x0D, to obtain the precise count of software change of PC (0x0C) and immediate branches (0x0D).