- 184.108.40.206. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
- 220.127.116.11. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
- 18.104.22.168. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
- 22.214.171.124. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
- 126.96.36.199. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
- 188.8.131.52. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
- 184.108.40.206. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
- 220.127.116.11. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
- 18.104.22.168. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
- 22.214.171.124. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
- 126.96.36.199. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
- 188.8.131.52. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
- 184.108.40.206. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
- 220.127.116.11. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
18.104.22.168. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D
The ISB is implemented as a branch in the Cortex* -A9 microarchitecture. Because ISB acts as a branch, events 0x0C (software change of PC) and 0x0D (immediate branch) are asserted when an ISB occurs, which is not compliant with the Arm* architecture.
The count of events 0x0C and 0x0D are not completely precise when using the Performance Monitor counters, because the ISB is counted together with the real software changes to the PC (for 0x0C) and immediate branches (0x0D).
- PMUEVENT relates to event 0x0C.
- PMUEVENT relates to event 0x0D.
You can count ISB instructions alone with event 0x90.
You can subtract this ISB count from the results you obtained in events 0x0C and 0x0D, to obtain the precise count of software change of PC (0x0C) and immediate branches (0x0D).
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