Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Public
Document Table of Contents
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1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code

Description

After enabling the L2 cache ECC feature, false ECC errors may occur.

Workaround

For affected devices, L2 cache ECC can be used and this issue avoided by setting the mpu_base_clk to a maximum frequency as follows:

  • Fast speed grade (-6) — 500 MHz
  • Mid speed grade (-7) — 400 MHz
  • Slow speed grade (-8) — 300 MHz
Note: If you are not using the L2 ECC feature, refer to the Cyclone V Device Datasheet for the maximum frequency of the mpu_base_clk.

Status

Affects: All Cyclone® V SX, ST and SE devices

Table 2.  Device and Revision FixedThis table identifies the fixed silicon by die revision for each device.
Device Revision without Fix Revision with Fix
5CSEA2 Rev A Rev B
5CSEA4 Rev A Rev B
5CSEA5 Rev A & B Rev C
5CSEA6 Rev A & B Rev C
5CSXC2 Rev A Rev B
5CSXC4 Rev A Rev B
5CSXC5 Rev A & B Rev C
5CSXC6 Rev A & B Rev C
5CSTD5 Rev A & B Rev C
5CSTD6 Rev A & B Rev C
Figure 1.  Intel Date Code Marking Format