Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault


Under certain conditions specific to the Cortex* -A9 microarchitecture, a write operation that updates a cacheable translation table entry might cause both the old and the new translation entry to be temporarily invisible to translation table walks, thus erroneously causing a translation fault.

This erratum requires the following conditions to happen:

  1. The processor has its data cache and MMU enabled.
  2. The TTB registers are set to work on memory regions with cacheable descriptors.
  3. The processor is updating an existing cacheable translation table entry, and this write operation hits in the L1 data cache.
  4. A hardware translation table walk is attempted. The hardware translation table walk can be due to either an instruction fetch, or to any other instruction execution that requires an address translation, including any load or store operation. This hardware translation walk must attempt to access the entry being updated in condition 2, and that access must hit in the L1 data cache.

In practice, this scenario can happen when an OS is changing the mapping of a physical page. The OS might have an existing mapping to a physical page (the old mapping), but wants to move the mapping to a new page (the new mapping). To do this, the OS might:

  • Write a new translation entry, without cancelling the old one. At this point, the physical page is accessible using either the old mapping or the new mapping.
  • Execute a DSB instruction followed by an ISB instruction pair, to ensure that the new translation entry is fully visible.
  • Remove the old entry.

Because of this erratum, this sequence might fail because it can happen that neither the new mapping, nor the old mapping, is visible after the new entry is written, causing a translation fault.


This erratum causes a translation fault.


The recommended workaround is to perform a clean and invalidate operation on the cache line that contains the translation entry before updating the entry, to ensure that the write operation misses in the data cache. This workaround prevents the microarchitectural conditions for this erratum from happening. Interrupts must be temporarily disabled so that no interrupt can be taken between the maintenance operation and the translation entry update to avoid the possibility of the interrupt service routine bringing the cache line back in the cache.

Another possible workaround is to place the translation table entries in non-cacheable memory areas, but this workaround is likely to have a noticeable performance penalty. Note that inserting a DSB instruction immediately after writing the new translation table entry significantly reduces the probability of encountering this erratum, but is not a complete workaround.


Category 3