Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value


PLD instructions prefetch and allocate any data marked as write-back (either write-allocate or non-write-allocate, shared or non-shared), regardless of the processor configuration settings, including the data cache enable bit value.


Because of this erratum, unexpected memory cacheability aliasing is created, which might result in various data consistency issues.

In practice, this erratum is unlikely to cause any significant issue. The data cache is likely to be enabled as soon as possible in most systems and not dynamically modified. Therefore, this erratum is likely to impact only boot-up code. This code is usually carefully controlled and does not usually contain any PLD instruction while the data cache is not enabled.


If this erratum impacts a system, a software workaround is available that is to set bit [20] in the undocumented Control register, which is placed in CP15 c15 0 c0 1.

This bit must be written with the following read-modify-write code sequence:

MRC p15,0,r0,c15,c0,1
ORR r0,r0,#0x00100000
MCR p15,0,r0,c15,c0,1

Setting this bit causes all PLD instructions to be treated as NOPs, with the consequence that code sequences that usually use the PLDs, such as the memcpy() routine, might suffer from a visible performance drop. Therefore, if this workaround is applied, Arm* strongly recommends restricting its use to periods of time where the data cache is disabled


Category 3