Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Public
Document Table of Contents

1.1.2.2. Fractional PLL Phase Alignment Error

Description

The fPLL has a silicon sensitivity that causes the static phase error to operate beyond the Quartus II software expectation. The frequency range and jitter performance of the fPLL meet the Cyclone® V Device Datasheet specifications. This sensitivity is a time zero failure, which means a design affected by this issue will show failure immediately upon a given device operation over expected operating conditions or will never show the issue.

The following usage modes may be affected:

  • When the fPLL is used for phase compensation. For example, applications that may use phase compensation include LVDS, board trace matching, or FPGA skew compensation, such as zero delay buffering.
  • Specific IP cores that require fPLL usage.
  • Inter-clock domain transfers involving fPLL usage.

Workaround

Customers can implement design techniques to mitigate inter-clock domain transfers and use the Intel® tool to evaluate fPLL usage and determine if designs may be affected by this issue.

If you believe your design is affected by this issue, please contact Intel® Premier Support for further assistance.

Status

Affects: Cyclone® V SX, ST, and SE devices

This issue is fixed in the silicon die revision shown below.

Table 5.  Fixed Silicon by Die Revision
Family Device Fixed Die Revision
Cyclone® V ST 5CSTD6 B
5CSTD5 B
Cyclone® V SX 5CSXC6 B
5CSXC5 B
5CSXC4 A
5CSXC2 A
Cyclone® V SE 5CSEA6 B
5CSEA5 B
5CSEA4 A
5CSEA2 A
Figure 3.  Intel Date Code Marking FormatThis figure explains the date code and revision marking format.