Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric


The default setting of the physel_x field in the System Manager EMAC Control Group's ctrl register cannot be used to configure an HPS I/O RMII PHY interface. Because the HPS I/O timings do not support RMII protocol, encodings 0x0 and 0x1 are the only valid values in the physel_x field. Selecting the 0x0 encoding routes the GMII/MII signals to the FPGA fabric only, and selecting the 0x1 encoding routes the RGMII interface to the HPS I/O only. If the physel_x encoding is left as 0x2, the HPS PHY interface does not function properly.


If an RMII PHY interface is required, the physel_x field should be set to 0x0 so that the GMII/MII signals are routed to the FPGA. You can design an RMII soft adaptor in the FPGA configuration file that converts these MII signals to an RMII PHY interface that is mapped to the FPGA I/O pins. Refer to the “Programming Model” section of the EMAC chapter in the Volume 3: Hard Processor System Technical Reference Manual for more information about how to initialize the EMAC Controller and interface.


Affects: All Cyclone® V SX, ST, and SE devices

Status: No planned fix