- 188.8.131.52. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock
- 184.108.40.206. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock
- 220.127.116.11. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption
- 18.104.22.168. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary
- 22.214.171.124. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault
- 126.96.36.199. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation
- 188.8.131.52. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements
- 184.108.40.206. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue
- 220.127.116.11. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded
- 18.104.22.168. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP
- 22.214.171.124. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value
- 126.96.36.199. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB
- 188.8.131.52. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock
- 184.108.40.206. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back
220.127.116.11. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric
The default setting of the physel_x field in the System Manager EMAC Control Group's ctrl register cannot be used to configure an HPS I/O RMII PHY interface. Because the HPS I/O timings do not support RMII protocol, encodings 0x0 and 0x1 are the only valid values in the physel_x field. Selecting the 0x0 encoding routes the GMII/MII signals to the FPGA fabric only, and selecting the 0x1 encoding routes the RGMII interface to the HPS I/O only. If the physel_x encoding is left as 0x2, the HPS PHY interface does not function properly.
If an RMII PHY interface is required, the physel_x field should be set to 0x0 so that the GMII/MII signals are routed to the FPGA. You can design an RMII soft adaptor in the FPGA configuration file that converts these MII signals to an RMII PHY interface that is mapped to the FPGA I/O pins. Refer to the “Programming Model” section of the EMAC chapter in the Volume 3: Hard Processor System Technical Reference Manual for more information about how to initialize the EMAC Controller and interface.
Affects: All Cyclone® V SX, ST, and SE devices
Status: No planned fix
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