Cyclone® V SX, ST and SE SoC Device Errata

ID 683618
Date 9/25/2015
Document Table of Contents 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded


When the processor is in the debug state, an instruction written to the Instruction Transfer Register (ITR) after a Load/Store instruction that has aborted, gets executed on clearing the SDABORT_l, instead of being discarded.

This erratum can occur under the following conditions:

  • The debugger has put the extDCCmode bits into stall mode.
  • A previously issued Load/Store instruction has generated a synchronous data abort (for example, an MMU fault).
  • For efficiency, the debugger does not read Debug Status and Control External (DBGDSCRext) register immediately, to see if the Load/Store has completed and has not aborted, but writes further instructions to the ITR, expecting them to be discarded if a problem occurs.
  • The debugger reads the Debug Status and Control (DBGDSCR) register at the end of the sequence and discovers the Load/Store aborted.
  • The debugger clears the SDABORT_l flag (by writing to the clear sticky aborts bit in Debug Run Control (DBGDRCR) register).

Under these conditions, the instruction that follows in the ITR might execute instead of being discarded.


Indeterminate failures can occur because of the instruction being executed when it should not. In most cases, it is unlikely that the failure will cause any significant issue.


There is a selection of workarounds with increasing complexity and decreasing impact. In each case, the impact is a loss of performance when debugging:

  • Do not use stall mode.
  • Do not use stall mode when doing Load/Store operations.
  • Always check for a sticky abort after issuing a Load/Store operation in stall mode (the cost of this probably means workaround number #2 is a preferred alternative).
  • Always check for a sticky abort after issuing a Load/Store operation in stall mode before issuing any further instructions that might corrupt an important target state (such as further Load/Store instructions, instructions that write to “live” registers such as VFP, CP15).


Category 3