Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.15. Variable Precision DSP

The Intel® Agilex™ FPGAs’ DSP blocks are based upon the variable precision DSP Architecture used in Intel’s previous generation devices. They feature hard fixed point and IEEE-754 compliant floating point capability which includes single-precision (32-bit arithmetic) FP32 floating point mode. New to Intel® Agilex™ FPGAs is the support for half-precision (16-bit arithmetic) FP16 floating point modes and BFLOAT16 floating-point format. The number of 9x9 multipliers have also increased, with two 9x9 multipliers for every one 18x19 multiplier, as compared to the previous generation of FPGAs.

The DSP blocks can be configured to support signal processing with precision ranging from 9x9 up to 54x54. A pipeline register has been added to increase the maximum operating frequency of the DSP block and reduce power consumption. In addition, dynamic switching of inputs to the multiplier is available through scanin and chainout features.

Figure 9. Low Precision Fixed Point Mode
Figure 10. Standard Precision Fixed Point Mode
Figure 11. High Precision Fixed Point Mode
Figure 12. Half Precision Floating Point Arithmetic 16-bit
Figure 13. Single Precision Floating Point Arithmetic 32-bit

Each DSP block can be independently configured at compile time as either quad 9x9, dual 18x19 or a single 27x27 multiply accumulate. With a dedicated 64-bit cascade bus, multiple variable precision DSP blocks can be cascaded to implement even higher precision DSP functions efficiently.

In floating point mode, each DSP block provides either single precision or half precision floating point (including FP16 and BFLOAT16) multiplier and adder. Floating point additions, multiplications, mult-adds and mult-accumulates are supported.

The following table shows how different precisions are accommodated within a DSP block, or by utilizing multiple blocks.

Table 23.   Variable Precision DSP Block Configuration
Multiplier Size DSP Block Resources Expected Usage
9x9 bits 1/4 of Variable Precision DSP Block Low precision fixed point
18x19 bits 1/2 of Variable Precision DSP Block Medium precision fixed point
27x27 bits 1 Variable Precision DSP Block High precision fixed point
19x36 bits 1 Variable Precision DSP Block with external adder Fixed point FFT
36x36 bits 2 Variable Precision DSP Blocks with external adder Very high precision fixed point
54x54 bits 4 Variable Precision DSP Blocks with external adder Double precision fixed point
Half Precision floating Point 1 variable precision DSP block (contains adder for two FP16 multipliers plus an accumulator) Half Precision Floating point
Single Precision floating point 1 variable precision DSP block (contains one FP32 multipliers with an accumulator) Single Precision Floating point

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