Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs

The Intel® Agilex™ D-Series FPGAs and SoCs added a new video IP, the MIPI* IP. The devices support MIPI* D-PHY* v2.5 at up to 3.5 Gbps for standard reference channel and up to 2.5 Gbps for long reference channel. The Intel® Agilex™ D-Series devices support MIPI* D-PHY* high-speed and low-power signaling modes without requiring external components.

Features of the MIPI* IP D-PHY* :

  • Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
  • Supports low-power and high-speed signaling up to 3.5 Gbps 0 per lane

The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Intel® Agilex™ D-Series devices in accordance to the following protocols:

  • Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
  • Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
Table 40.   MIPI* CSI-2 and DSI-2 Performance in Intel® Agilex™ D-Series FPGAs and SoCs
MIPI* Protocol Performance
CSI-2
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
DSI-2
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
Figure 17.  MIPI* Receiver Block Diagram


Figure 18.  MIPI* Transmitter Block Diagram


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