15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs
Features of the MIPI* IP D-PHY* :
- Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
- Supports low-power and high-speed signaling up to 3.5 Gbps 0 per lane
The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Intel® Agilex™ D-Series devices in accordance to the following protocols:
- Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
- Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
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