Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 10/31/2023
Public
Document Table of Contents

15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs

The Intel® Agilex™ D-Series FPGAs and SoCs added a new video IP, the MIPI* IP. The devices support MIPI* D-PHY* v2.5 at up to 3.5 Gbps for standard reference channel and up to 2.5 Gbps for long reference channel. The Intel® Agilex™ D-Series devices support MIPI* D-PHY* high-speed and low-power signaling modes without requiring external components.

Features of the MIPI* IP D-PHY* :

  • Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
  • Supports low-power and high-speed signaling up to 3.5 Gbps 0 per lane

The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Intel® Agilex™ D-Series devices in accordance to the following protocols:

  • Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
  • Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
Table 40.   MIPI* CSI-2 and DSI-2 Performance in Intel® Agilex™ D-Series FPGAs and SoCs
MIPI* Protocol Performance
CSI-2
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
DSI-2
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
Figure 17.  MIPI* Receiver Block Diagram


Figure 18.  MIPI* Transmitter Block Diagram