Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 10/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

1.5.3. Intel® Agilex™ M-Series SoC FPGAs

Table 11.   Intel® Agilex™ M-Series SoC FPGAs Family Plan—Part 1
Intel® Agilex™ M-Series Device Names Logic Elements (LE) Adaptive Logic Modules (ALM) M20K Blocks M20K Mbits MLAB Counts MLAB Mbits HBM2e DRAM GBytes Variable Precision DSP Blocks 18x19 Multipliers
AGM 032 3,245,000 1,100,000 15,932 311 55,000 33 16/32 9,375 18,750
AGM 039 3,851,520 1,305,600 18,960 370 65,280 40 16/32 12,300 24,600
Table 12.   Intel® Agilex™ M-Series SoC FPGAs Family Plan—Part 2
Intel® Agilex™ M-Series Device Names Crypto Blocks

R-Tile

PCIe Blocks

22

Compute Express Link (CXL) Lanes

23

F-Tile Ethernet 400 GbE

24

F-Tile PCIe

25

F-Tile High Speed

(FHT)

116 Gbps

26

F-Tile General Purpose

(FGT)

58 Gbps

27

HPS
AGM 032 0 1 16 (Available in 3687A package) 4 (Maximum of four F-tiles in 3184B package) 4 (Maximum of four PCIe controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

 Yes
AGM 039 0 1 16 (Available in 3687A package) 4 (Maximum of four F-tiles in 3184B package) 4 (Maximum of four PCIe controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

 Yes
Table 13.   Intel® Agilex™ M-Series FPGAs with F-Tile Package Options and I/O Pins
  • Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 56G (116G).
  • Example: If an entry in the table below contains 720(360)/64(48)/8(8), it means, 720 GPIO of which 360 are LVDS; sixty-four 32G NRZ channels and forty-eight 58G PAM4 channels; eight 56G NRZ channels and eight 116G PAM4 channels.
Intel® Agilex™ M-Series Device Names 3184B 28
AGM 032 720(360)/64(48)/8(8)
AGM 039 720(360)/64(48)/8(8)
Table 14.   Intel® Agilex™ M-Series FPGAs with F-Tile and R-Tile Package Options and I/O Pins
  • Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 58G (116G) / R-Tile 32G PCIe (CXL) Lanes.
  • Example: If an entry in the table below contains 768(384)/48(36)/8(8)/16(16)), it means: 768 GPIO of which 384 are LVDS; forty-eight 32G NRZ channels or thirty-six 58G PAM4 channels; eight 58G NRZ channels or eight 116G PAM4 channels; sixteen up to 32G/lane PCIe or sixteen lanes of CXL.
Intel® Agilex™ M-Series Device Names 3687A 29
AGM 032 768(384)/48(36)/8(8)/16(16)
AGM 039 768(384)/48(36)/8(8)/16(16)
Table 15.   Intel® Agilex™ M-Series FPGAs with F-Tile and HBM2e Package Options and I/O Pins
  • Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 56G (116G).
  • Example: If an entry in the table below contains 768(384)/48(36)/8(8), it means: 768 GPIO of which 384 are LVDS; forty-eight 32G NRZ channels or thirty-six 58G PAM4 channels; eight 56G NRZ channels or eight 116G PAM4 channels.
Intel® Agilex™ M-Series Device Names 4700B 30 31
AGM 032 768(384)/64(48)/8(8)
AGM 039 768(384)/64(48)/8(8)
Table 16.   Intel® Agilex™ M-Series FPGAs with F-Tile, R-Tile, and HBM2e Package Options and I/O Pins
  • Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 58G (116G) / R-Tile 32G PCIe (CXL) Lanes.
  • Example: If an entry in the table below contains 768(384)/48(36)/8(8)/16(0), it means: 768 GPIO of which 384 are LVDS; forty-eight 32G NRZ channels or thirty-six 58G PAM4 channels; eight 58G NRZ channels or eight 116G PAM4 channels; sixteen up to 32G/lane PCIe or zero lanes of CXL.
Intel® Agilex™ M-Series Device Names 4700A 32 31
AGM 032 768(384)/48(36)/8(8)/16(0)
AGM 039 768(384)/48(36)/8(8)/16(0)
22 Maximum R-Tile PCIe hard IP blocks (Gen5 x16) or Bifurcateable 2x PCIe Gen5 x8 (EP) or 4x Gen5 x4 (RP)
23 Maximum CXL lanes for Intel® Xeon® Scalable Processor
24 Maximum F-Tile 10/25/40/50/100/200/400G Ethernet MAC + FEC hard IP blocks
25 Maximum F-Tile PCIe hard IP blocks (Gen4 x16), or Bifurcateable 2x PCIe Gen4 x8 (EP), or 4x Gen4 x4 (RP)
26 Maximum F-Tile High Speed (FHT) Transceiver Channels PAM4 (up to 116 Gbps) – RS and KP FEC NRZ (up to 58 Gbps)
27 Maximum F-Tile General Purpose (FGT) Transceiver Channels PAM4 (up to 58 Gbps) – RS and KP FEC NRZ (up to 32 Gbps)
28 (F-Tile x 4) (Dimension: 56 mm x 45 mm, Pitch (mm): 0.92 Hex)
29 (F-Tile x 3 + R-Tile) (Dimension: 56 mm x 52.5 mm, Pitch (mm): 0.92 Hex)
30 (F-Tile x 3 + HBM2e) (Dimension: 56 mm x 66 mm, Pitch (mm): 0.92 Hex)
31 Devices in 4700A/B packages are available with 16 GB or 32 GB in-package HBM2e memory
32 (F-Tile x 3 + R-Tile + HBM2e) (Dimension: 56 mm x 66 mm, Pitch (mm): 0.92 Hex)
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