Intel® Agilex™ FPGAs and SoCs Device Overview

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ID 683458
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview
1. Overview of the Intel® Agilex™ FPGAs and SoCs
1.1. Key Features and Innovations in Intel® Agilex™ FPGAs and SoCs 1.2. Intel® Agilex™ FPGA and SoC Block Diagram 1.3. Intel® Agilex™ FPGA and SoC Summary of Features 1.4. Additional Features for Intel® Agilex™ SoCs
2. Intel® Agilex™ FPGAs and SoCs Family Plan
2.1. Intel® Agilex™ F-Series FPGAs and SoCs 2.2. Intel® Agilex™ I-Series FPGAs and SoCs 2.3. Intel® Agilex™ M-Series FPGAs and SoCs 2.4. Intel® Agilex™ D-Series FPGAs and SoCs 2.5. Available Options
10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs
10.1. Features of the Hard Memory Controller
12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs
12.1. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs 12.2. Monolithic Transceivers in Intel® Agilex™ D-Series FPGAs and SoCs
12.1. Heterogeneous 3D SiP Transceivers in Intel® Agilex™ F-Series, I-Series, and M-Series FPGAs and SoCs
12.1.1. E-Tile Transceivers 12.1.2. P-Tile Transceivers 12.1.3. F-Tile Transceivers 12.1.4. R-Tile Transceivers
12.1.1. E-Tile Transceivers
12.1.1.1. PMA Features in E-Tile Transceivers 12.1.1.2. PCS Features in E-Tile Transceivers
12.2. Monolithic Transceivers in Intel® Agilex™ D-Series FPGAs and SoCs
12.2.1. PMA Features in Intel® Agilex™ D-Series Transceivers 12.2.2. PCS Features in Intel® Agilex™ D-Series Transceivers 12.2.3. Transceiver PLL in Intel® Agilex™ D-Series FPGAs and SoCs
21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs
21.1. Additional SEU Mitigation Features in Intel® Agilex™ D-Series FPGAs and SoCs
1. Overview of the Intel® Agilex™ FPGAs and SoCs
2. Intel® Agilex™ FPGAs and SoCs Family Plan
3. Second Generation Intel® Hyperflex™ Core Architecture
4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs
5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs
6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs
7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs
8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs
9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs
10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs
11. Hard Processor System in Intel® Agilex™ SoCs
12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs
14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs
15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs
16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs
17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs
18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs
19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs
20. Device Security for Intel® Agilex™ FPGAs and SoCs
21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs
22. Power Management for Intel® Agilex™ FPGAs and SoCs
23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs
24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.13. Internal Embedded Memory

Intel® Agilex™ devices contain three types of embedded memory blocks:

  • MLAB (640 bits)
  • M20K (20 Kbits)
  • eSRAM (18 Mbits—not available in Intel® Agilex™ M-Series devices)

The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB internal embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register.

In addition, some Intel® Agilex™ devices (refer to product tables for details) also include 18 Megabit (Mb) eSRAM blocks with stitching support. These blocks are large size, fast path, low latency, high bandwidth on-chip memory block and include ECC.

These memory blocks are highly flexible and support a number of memory configurations as shown in the table below.

Table 22.  Internal Embedded Memory Block Configuration
MLAB (640 bits) M20K (20 Kbits) eSRAM (18 Mbits)

64 x 10 (supported through emulation)

32 x 20

2K x 10 (or x8)

1K x 20 (or x 16)

512 x 40 (or x32)

8 channels of 2.25Mb (18Mb) (each channel contains 32 banks of 72 x 1K memory)
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