Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.5.2. Intel® Agilex™ I-Series SoC FPGAs

Table 7.   Intel® Agilex™ I-Series SoC FPGAs Family Plan Part-1
Intel® Agilex™ I-Series Device Names Logic Elements (LE) Adaptive Logic Modules (ALM) eSRAM Blocks eSRAM Mbits M20K Blocks M20K Mbits MLAB Counts MLAB Mbits Variable Precision DSP Blocks 18x19 Multipliers
AGI 019 1,918,975 650,500 1 18 8,500 166 35,525 20 1,354 2,708
AGI 023 2,308,080 782,400 1 18 10,464 204 39,120 24 1,640 3,280
AGI 022 2,208,075 748,500 0 0 10,900 212 37,425 23 6,250 12,500
AGI 027 2,692,760 912,800 0 0 13,272 259 45,640 28 8,528 17,056
AGI 035 3,540,000 1,200,000 3 54 14,931 292 60,000 37 9,594 19,188
AGI 040 4,047,400 1,372,000 3 54 19,908 389 68,600 42 12,792 25,584
Note: For Intel® Agilex™ FPGA devices, the PCIe* blocks are supported in the tile locations 15A, 14C and 15C. CXL is only supported on location 14C and 15C in 2957A package.
Table 8.   Intel® Agilex™ I-Series SoC FPGAs Family Plan Part-2
Intel® Agilex™ I-Series Device Names Crypto Blocks

R-Tile

PCIe Blocks

12

Compute Express Link (CXL) Lanes

13

F-Tile

Ethernet

400 GbE

14

F-Tile

PCIe

15

F-Tile High Speed

(FHT)

116 Gbps

16

F-Tile General Purpose

(FGT)

58 Gbps

17

HPS

AGI 019 2 1 16 4 (Maximum of four F-Tiles in 3184B package) 4 (Maximum of four PCIe* controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

Yes
AGI 023 2 1 16 4 (Maximum of four F-Tiles in 3184B package) 4 (Maximum of four PCIe* controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

Yes
AGI 022 0 3 32 4 (Maximum of four F-Tiles in 3184B package) 4 (Maximum of four PCIe* controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

Yes
AGI 027 0 3 32 4 (Maximum of four F-Tiles in 3184B package) 4 (Maximum of four PCIe* controllers in 3184B package)

8x PAM4/

8x NRZ

48x PAM4/

64x NRZ

Yes
AGI 035 4 6 (Maximum of six F-Tiles in 3948A package) 6 (Maximum of six PCIe* controllers in 3948A package)

24x PAM4/

24x NRZ

72x PAM4/

96x NRZ

No
AGI 040 4 6 (Maximum of six F-Tiles in 3948A package) 6 (Maximum of six PCIe* controllers in 3948A package)

24x PAM4/

24x NRZ

72x PAM4/

96x NRZ

No
Table 9.   Intel® Agilex™ I-Series FPGAs with F-Tile Package Options and I/O Pins

Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 56G (116G).

Example: If an entry in the table below contains 720(360)/64(48)/8(8), it means, 720 GPIO of which 360 are LVDS; sixty-four 32G NRZ channels and forty-eight 58G PAM4 channels; eight 56G NRZ channels and eight 116G PAM4 channels.

Intel® Agilex™ I-Series Device Names 3184B 18 3948A 19
AGI 019 480(240)/64(48)/8(8)
AGI 023 480(240)/64(48)/8(8)
AGI 022 720(360)/64(48)/8(8)
AGI 027 720(360)/64(48)/8(8)
AGI 035 576(288)/96(72)/24(24)
AGI 040 576(288)/96(72)/24(24)
Table 10.   Intel® Agilex™ I-Series FPGAs with F-Tile and R-Tile Package Options and I/O Pins

Key: GPIO (LVDS) / F-Tile 32G (58G) / High Speed 58G (116G) / R-Tile 32G PCIe (CXL) Lanes.

Example: If an entry in the table below contains 720(360)/16(12)/4(4)/48(48), it means, 720 GPIO of which 360 are LVDS; sixteen 32G NRZ channels or twelve 58G PAM4 channels; Four 58G NRZ channels or four 116G PAM4 channels; forty-eight up to 32G/lane PCIe or forty-eight lanes of CXL.

Intel® Agilex™ I-Series Device Names 1805A 20 2957A 21
AGI 019 480(240)/16(12)/0(0)/16(0)
AGI 023 480(240)/16(12)/0(0)/16(0)
AGI 022 720(360)/16(12)/4(4)/48(32)
AGI 027 720(360)/16(12)/4(4)/48(32)
12 Maximum R-Tile PCIe hard IP blocks (Gen5 x16) or Bifurcateable 2x PCIe Gen5 x8 (EP) or 4x Gen5 x4 (RP)
13 Maximum CXL lanes for Intel® Xeon® Scalable Processor
14 Maximum F-Tile 10/25/40/50/100/200/400G Ethernet MAC + FEC hard IP blocks
15 Maximum F-Tile PCIe* hard IP blocks (Gen4 x16 ) or Bifurcateable 2x PCIe Gen4 x8 (EP) or 4x Gen4 x4 (RP)
16 Maximum F-Tile High Speed (FHT) Transceiver Channels PAM4 (up to 116 Gbps) – RS and KP FEC NRZ (up to 58 Gbps)
17 Maximum F-Tile General Purpose (FGT) Transceiver Channels PAM4 (up to 58 Gbps) – RS and KP FEC NRZ (up to 32 Gbps)
18 (F-Tile x4) (Dimension: 56 mm x 45 mm, Pitch (mm): 0.92 Hex)
19 (F-Tile x6) (Dimension: 56 mm x 56 mm, Pitch (mm): 0.92 Hex)
20 (F-Tile + R-Tile) (Dimension: 42.5 mm x 42.5 mm, Pitch (mm): 1.025 Hex)
21 (F-Tile + R-Tile x 3) (Dimension: 56 mm x 45 mm, Pitch (mm): 1.0/0.92 Hex)

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