Agilex™ 7 FPGAs and SoCs Device Overview

ID 683458
Date 4/01/2024
Document Table of Contents

1.17. Hard Processor System (HPS)

The Intel® Agilex™ SoC Hard Processor System (HPS) is Intel’s industry leading third generation HPS. The HPS is a quad-core Arm* Cortex* -A53, which allows users to easily migrate existing SoC designs from Intel® Stratix® 10 SoCs to Intel® Agilex™ SoC.

The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit. These architecture improvements ensure that SoCs meet the requirements of current and future embedded markets, including wireless and wireline communications, datacenter acceleration, and numerous military applications.

Figure 14. HPS Block Diagram

Key Features of the Intel® Agilex™ HPS

Table 24.  Key Feature Summary



Quad-core ARM Cortex-A53 MPCore processor unit
  • 2.3 MIPS/MHz instruction efficiency
  • CPU frequency up to 1.4 GHz
  • At 1.4 GHz total performance of 13,800 MIPS
  • ARMv8-A architecture
  • Runs 64-bit and 32-bit ARM instructions
  • 16-bit and 32-bit Thumb instructions for 30% reduction in memory footprint
  • Jazelle® RCT execution architecture with 8-bit Java bytecodes
  • Superscalar, variable length, out-of-order pipeline with dynamic branch prediction
  • Improved ARM NEON™ media processing engine
  • Single and double-precision floating-point unit
  • CoreSight™ debug and trace technology
System Memory Management Unit
  • Enables a unified memory model and extends hardware virtualization into peripherals implemented in the FPGA fabric
Cache Coherency Unit
  • Changes in shared data stored in cache are propagated throughout the system providing bi-directional coherency for co-processing elements.
Cache Memory
  • L1 Cache
    • 32 KB of instruction cache with parity check
    • 32 KB of L1 data cache with ECC
    • Parity checking
  • L2 Cache
    • 1 MB shared
    • 8-way set associative
    • SEU Protection with parity on TAG ram and ECC on data RAM
    • Cache lockdown support
On-Chip Memory
  • 256 KB of scratch on-chip RAM
External SDRAM and Flash Memory Interfaces for HPS
  • Hard memory controller with support for DDR4
    • 40-bit (32-bit + 8 bit ECC) with select packages supporting 72-bit (64 bit + 8 bit ECC)
    • Support for up to 3200 Mbps DDR4
    • Error correction code (ECC) support including calculation, error correction, write-back correction, and error counters
    • Software Configurable Priority Scheduling on individual SDRAM bursts
    • Fully programmable timing parameter support for all JEDEC-specified timing parameters
    • Multiport front-end (MPFE) scheduler interface to the hard memory controller, which supports the AXI® Quality of Service (QoS) for interface to the FPGA fabric
  • NAND flash controller
    • ONFI 1.0
    • Integrated descriptor based with DMA
    • Programmable hardware ECC support
    • Support for 8 and 16 bit Flash devices
  • Secure Digital SD/SDIO/MMC controller
    • eMMC 4.5
    • Integrated descriptor based DMA
    • CE-ATA digital commands supported
    • 50 MHz operating frequency
  • Direct memory access (DMA) controller
    • 8-channel
    • Supports up to 32 peripheral handshake interface
Communication Interface Controllers
  • Three 10/100/1000 Ethernet media access controls (MAC) with integrated DMA
    • Supports RGMII and RMII external PHY Interfaces
    • Option to support other PHY interfaces through FPGA logic
      • GMII
      • MII
      • RMII (requires MII to RMII adapter)
      • RGMII (requires GMII to RGMII adapter)
      • SGMII (requires GMII to SGMII adapter)
    • Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchronization
    • Supports IEEE 802.1Q VLAN tag detection for reception frames
    • Supports Ethernet AVB standard
  • Two USB On-the-Go (OTG) controllers with DMA
    • Dual-Role Device (device and host functions)
      • High-speed (480 Mbps)
      • Full-speed (12 Mbps)
      • Low-speed (1.5 Mbps)
      • Supports USB 1.1 (full-speed and low-speed)
    • Integrated descriptor-based scatter-gather DMA
    • Support for external ULPI PHY
    • Up to 16 bidirectional endpoints, including control endpoint
    • Up to 16 host channels
    • Supports generic root hub
    • Configurable to OTG 1.3 and OTG 2.0 modes
  • Five I2C controllers (three can be used by EMAC for MIO to external PHY)
    • Support both 100 Kbps and 400 Kbps modes
    • Support both 7 bit and 10 bit addressing modes
    • Support Master and Slave operating mode
  • Two UART 16550 compatible
    • Programmable baud rate up to 115.2 Kbaud
  • Four serial peripheral interfaces (SPI) (2 Masters, 2 Slaves)
    • Full and Half duplex
Timers and I/O
  • Timers
    • 4 general-purpose timers
    • 4 watchdog timers
  • 48 HPS direct I/O allow HPS peripherals to connect directly to I/O
  • Up to two IO96 banks may be assigned to HPS for HPS DDR access
Interconnect to Logic Core
  • HPS-to-FPGA Bridge
    • Allows HPS bus masters to access bus slaves in FPGA fabric
    • Configurable 32, 64, or 128 bit AMBA AXI interface allows high-bandwidth HPS master transactions to FPGA fabric
  • HPS-to-SDM and SDM-to-HPS Bridges
    • Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS
  • Light Weight HPS-to-FPGA Bridge
    • Light weight 32 bit AXI interface suitable for low-latency register accesses from HPS to soft peripherals in FPGA fabric
  • FPGA-to-SoC Bridge
    • Configurable 128, 256, 512 bit ACE-Lite interface
    • Up to 256-bit FPGA-to-SoC targeting HPS
    • Up to 512-bit FPGA-to-SoC targeting DDR