Agilex™ 7 FPGAs and SoCs Device Overview

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ID 683458
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 7 FPGAs and SoCs 2. Agilex™ 7 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs 7. Core Clock Network in Agilex™ 7 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs 9. I/O PLLs in Agilex™ 7 FPGAs and SoCs 10. External Memory Interface in Agilex™ 7 FPGAs and SoCs 11. Hard Processor System in Agilex™ 7 SoCs 12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series 14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series 15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs 18. Device Security for Agilex™ 7 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs 20. Power Management for Agilex™ 7 FPGAs and SoCs 21. Software and Tools for Agilex™ 7 FPGAs and SoCs 22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 7 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 7 FPGAs and SoCs 1.2. Agilex™ 7 FPGAs and SoCs Block Diagram 1.3. Agilex™ 7 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 7 SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan x
2.1. Agilex™ 7 FPGAs and SoCs F-Series 2.2. Agilex™ 7 FPGAs and SoCs I-Series 2.3. Agilex™ 7 FPGAs and SoCs M-Series 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs x
12.1. E-Tile Transceivers 12.2. P-Tile Transceivers 12.3. F-Tile Transceivers 12.4. R-Tile Transceivers
12.1. E-Tile Transceivers x
12.1.1. PMA Features in E-Tile Transceivers 12.1.2. PCS Features in E-Tile Transceivers
1. Overview of the Agilex™ 7 FPGAs and SoCs
2. Agilex™ 7 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 7 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 7 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 7 FPGAs and SoCs
7. Core Clock Network in Agilex™ 7 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 7 FPGAs and SoCs
9. I/O PLLs in Agilex™ 7 FPGAs and SoCs
10. External Memory Interface in Agilex™ 7 FPGAs and SoCs
11. Hard Processor System in Agilex™ 7 SoCs
12. Heterogeneous 3D SiP Transceivers in Agilex™ 7 FPGAs and SoCs
13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Agilex™ 7 FPGAs and SoCs M-Series
14. High-Performance Crypto Blocks in Agilex™ 7 FPGAs and SoCs F-Series and I-Series
15. Configuration via Protocol Using PCIe* for Agilex™ 7 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 7 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 7 FPGAs and SoCs
18. Device Security for Agilex™ 7 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 7 FPGAs and SoCs
20. Power Management for Agilex™ 7 FPGAs and SoCs
21. Software and Tools for Agilex™ 7 FPGAs and SoCs
22. Revision History for the Agilex™ 7 FPGAs and SoCs Device Overview

1.8. Intel® Agilex™ FPGA Transceivers

Intel® Agilex™ FPGAs offer different transceivers that are optimized for a wide variety of applications, ranging from 1 Gbps to 32 Gbps in NRZ mode and 2 Gbps to 58 Gbps in PAM4 and 116 Gbps PAM4.

The following tables below summarizes the transceivers capabilities in each tile, and the availability of the tiles in each device family.

Table 17.  Tile Names and Capabilities
Tile Maximum Data Rate and Channel Count Hard IP (HIP) Applications
E-Tile

12 x 58G PAM4

or

24 x 28.9G NRZ

10/25/100GE MAC, PCS and RS-FEC (528,514) , RS-FEC (544,514)

General Purpose Transceiver with multi-protocol support for CEI, Ethernet, CPRI, FlexE, Interlaken, Fibre Channel, SRIO, Serial Lite, OTN, JESD204B/C, FlexO, IEEE1588

P-Tile

16 x 16G NRZ

PCIe Gen4 x16 with 8 PF/2K VF SR-IOV EP/RP

PCIe Gen4 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP , Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV and Shared Virtual Memory

F-Tile

4 x 116G PAM4,

12 x 58G PAM4

or

16 x 32G NRZ

10/25/40/50/100/200/400GE MAC, PCS, and KR/KP RS-FEC

PCIe Gen4 x16 with 8 PF/2K VF SR-IOV EP/RP

General Purpose Transceiver with multi-protocol support for CEI, Ethernet, CPRI, FlexE, 300G Interlaken, Fibre Channel, SRIO, Serial Lite, OTN, JESD204B/C, IEEE1588, FlexO, GPON, SDI, Vby1, HDMI, CvP, Display Port, P-Tile PCIe features plus Precise Time Management and PMA direct mode

R-Tile

16 x 32G NRZ

PCIe Gen5 x16 with 8 PF/2K VF SR-IOV EP/RP

Compute Express Link (CXL)

PCIe Gen5 x16 including port bifurcation support for 2x8 EP or 4x4 RP, CvP, Autonomous HIP, SR-IOV 8PF / 2kVF, VirtIO, Scalable IOV, and Shared Virtual Memory, separate header and payload interfaces on user interface, Precise Time Management, PIPE Direct

Table 18.  Tile Availability in Device Family
Tile Name Intel® Agilex™ F-Series FPGAs Intel® Agilex™ I-Series FPGAs Intel® Agilex™ M-Series FPGAs
E-Tile Y — —
P-Tile Y — —
F-Tile Y Y Y
R-Tile — Y Y

Section Content
E-Tile Transceivers
P-Tile Transceivers
F-Tile Transceivers
R-Tile Transceivers

Level Two Title