Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.3. Intel® Agilex™ FPGA and SoC Summary of Features

The Intel® Agilex™ FPGAs and SoCs share the same high performance core fabric and common features.
Table 2.   Feature Summary
Feature Description
Packaging F-Series

I-Series

M-Series

  • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • Mixture of ball pitch FBGA packages, 1,025 mm, 0.92 mm, and several mixed pitch packages
  • Rectangular package with hexagonal ball grid (mixture of grid and hexagonal patterns)
D-Series
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • "Balls anywhere" package design for smaller package form factor and reduced number of PCB layers
High performance core fabric
  • Second Generation Intel® Hyperflex™ core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
  • Enhanced adaptive logic module (ALM)
  • Improved multi-track routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration
Internal memory blocks
  • Multi-level on-chip memory hierarchy
  • M20K—20 kilobits with hard error correction code (ECC) support
  • MLAB—640-bit distributed LUTRAM

F-Series and I-Series only

eSRAM—18 Mb embedded memory block with hard ECC support
Variable precision DSP blocks
  • Variable precision DSP blocks with hard IEEE 754-compliant floating-point units, including support for:
    • Single-precision FP32 (32-bit arithmetic)
    • Half-precision FP16 (16-bit arithmetic) floating point modes
    • Tensor floating point FP19 (19-bit arithmetic) floating point modes
    • BFLOAT16 floating-point format
  • Supports signal processing with precision ranging from 9×9 up to 54×54
  • Native 27×27, 18×19, and 9×9 multiplication modes
  • 64-bit accumulator and cascade for systolic 200 GbE finite impulse responses (FIRs)
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • 2× additional pipeline register increases performance and reduces power consumption

D-Series only

  • Supports single-precision FP32
  • Supports half-precision FP19
  • High-performance AI Tensor blocks:
    • Enables high-performance compute density of FPGA fabric Tera Operations Per Second (TOPS)
    • Up to 57 INT8 TOPS for AI workloads
    • Hardware programmable for AI with customized workloads
    • Supports push-button flow from industry standard frameworks, such as TensorFlow* , to FPGA bitstream
  • Every DSP block supports INT16 complex multiplication mode
Core clock networks
  • Programmable clock tree synthesis—backwards compatible with global, regional and peripheral clock networks
  • Synthesize clocks where needed only—minimizes dynamic power
F-Series

I-Series

  • 800 MHz LVDS interface clocking—supports 1,600 Mbps LVDS interface through the 1.5 V True Differential Signaling (TDS) standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 1,600 MHz external memory interface clocking, supports 3,200 Mbps DDR4 interface
D-Series
  • 800 MHz LVDS interface clocking—supports 1,600 Mbps LVDS interface through the 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 2,000 MHz external memory interface clocking, supports 4,000 Mbps DDR5 interface
M-Series
  • 800 MHz LVDS interface clocking—supports 1,600 Mbps LVDS interface through the 1.5 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 2,800 MHz external memory interface clocking, supports 5,600 Mbps DDR5 interface
General purpose I/Os General

F-Series

I series

M-Series

  • Over 700 total GPIOs available
  • 1.6 Gbps 1.5 V TDS compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 1.2 V single-ended LVCMOS/LVTTL interfacing
  • 1.8 V, 2.5 V, and 3.3 V single-ended LVCMOS/LVTTL I/O
  • On-chip termination (OCT)

D-Series

  • Over 400 total GPIOs available
  • 1.6 Gbps 1.3 V TDS standard compatible with LVDS, RSDS, mini-LVDS, and LVPECL standards
  • 1.05 V, 1.1 V, and 1.2 V single-ended LVCMOS/LVTTL interfacing
  • 1.8 V, 2.5 V, and 3.3 V single-ended LVCMOS/LVTTL I/O
  • On-chip termination (OCT)

External memory interface

(Hard IP)

F-Series

I-Series

1,600 MHz (3,200 Mbps) DDR4 external memory interface

M-Series

  • 1,600 MHz (3,200 Mbps) DDR4 external memory interface
  • 2,800 MHz (5,600 Mbps) DDR5 external memory interface
  • 2,750 MHz (5,500 Mbps) LPDDR5 external memory interface

D-Series

  • 2,000 MHz (4,000 Mbps) DDR5 external memory interface
  • 2,133 MHz (4,267 Mbps) LPDDR5 external memory interface
  • 1,600 MHz (3,200 Mbps) DDR4 external memory interface
  • 2,133 MHz (4,267 Mbps) LPDDR4/4X external memory interface
MIPI* D-Series MIPI* D-PHY* v2.5 at up to 3.5 Gbps 7 per lane
Phase locked loops (PLL) I/O PLL
  • Integer PLLs adjacent to general purpose I/Os
  • Precision frequency synthesis
  • Clock delay compensation
  • Zero-delay buffering
  • Support external memory and LVDS-compatible interface

Transmit PLLs

(TX PLLs)

  • Precise fractional synthesis
  • Ultra low jitter with LC tank-based PLL
  • Supports transceiver interfaces
System PLL D-Series
  • One System PLL per bank
  • Integer mode
  • Precision frequency synthesis
  • Supports transceiver-to-fabric interface
  • You can repurpose the System PLL for core usage if it is not used by the transceiver
Memory controller support Multiple hard IP instantiations in each device
F-Series

I-Series

  • DDR4 hard memory controller
  • QDR IV using soft memory controller
M-Series
  • DDR5/LPDDR5/DDR4 hard memory controller
  • QDRIV support using soft memory controller
  • Hard memory network-on-chip (NoC)
D-Series
  • DDR5 hard memory controller
  • LPDDR5 hard memory controller
  • DDR4 hard memory controller
  • LPDDR4/4X hard memory controller
High-bandwidth memory M-Series only
  • In-package HBM2E memory options
  • Up to 32 GB of high bandwidth memory
Memory NoC M-Series only
  • Hardened memory network-on-chip (NoC) enabling high bandwidth data flow between the FPGA fabric and the NoC-attached memories without using FPGA resources
  • Supports over 1 terabytes per second (TBps) of aggregate memory bandwidth
High-performance crypto blocks8
  • Supports AES and SM4 encryption standards
  • Supports GCM and XTS modes of operation
Transceivers PCIe* P-Tile

F-Tile

D-Series

PCIe* rates up to PCIe* 4.0, 16 Gbps NRZ
R-Tile
  • PCIe* rates up to PCIe* 5.0, 32 Gbps NRZ
  • Compute Express Link* ( CXL* ) support
Networking E-Tile
  • Continuous operating range of 1 Gbps to 28.9 Gbps NRZ and 2 Gbps to 58 Gbps PAM4
  • Insertion loss compliant to 802.3bj, CEI 25G-LR, and CEI 56G-LR
  • Oversampling capability for data rates below 1 Gbps
  • ATX transmit PLLs (LC-PLL) with user-configurable fractional synthesis capability
  • XFP, QSFP-DD, OSFP, QSFP or QSFP28, QSFP56, SFP+, SFP28, SFP56, and CFP or CFP2 or CFP4 optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels
  • On-chip instrumentation (Eye Viewer non-intrusive data eye monitoring)
F-Tile
  • General purpose transceiver block (FGT) with continuous operating range of 1 Gbps to 32 Gbps NRZ and 20 Gbps to 58 Gbps PAM4
  • High speed transceiver block (FHT) with operating ranges of:
    • 24 Gbps to 29 Gbps NRZ and PAM4
    • 48 Gbps to 58 Gbps NRZ and PAM4
    • 96 Gbps to 116 Gbps PAM4
  • The F-Tiles in these devices have the following transceivers:
    • F-Tiles in Intel® Agilex™ I-Series—FHT and FGT transceivers
    • F-Tiles in Intel® Agilex™ M-Series—FHT and FGT transceivers
    • F-Tiles in Intel® Agilex™ F-Series—FGT transceivers only
D-Series
  • Continuous operating range of 1 Gbps to 28.1 Gbps NRZ
  • Insertion loss compliant to 802.3bj and CEI 25G-LR standards
  • Oversampling capability for data rates below 1 Gbps
  • SFP+ optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic reconfiguration of individual transceiver channels
  • On-chip instrumentation ( Intel® Quartus® Prime Eye Viewer with non-destructive eye height and destructive eye width margining)
Transceiver hard IP PCIe*
  • Multiple hard IP instantiations in each device

P-Tile

F-Tile

  • Up to PCIe* 4.0 ×16 EP and RP
  • Port bifurcation support: 2×8 endpoint or 4×4 root port
  • TL bypass feature
  • Single-root I/O virtualization (SR-IOV): 8 physical functions or 2K virtual functions
  • VirtIO support
  • Scalable IOV
  • Shared virtual memory
R-Tile
  • Up to PCIe* 5.0 ×16 EP and RP
  • Port bifurcation support: 2×8 endpoint or 4×4 root port
  • TL bypass Feature
  • SR-IOV: 8 physical functions or 2K virtual functions
  • VirtIO support
  • Scalable IOV
  • Shared Virtual Memory
  • PIPE Direct mode
  • Precise Time Management
D-Series
  • Up to PCIe* 4.0 ×8 EP and RP
  • Port bifurcation support: 4×8 root port or endpoint, or (4×4)+(4×4) root port or endpoint
  • TLP bypass feature
  • SR-IOV
  • Precise time management
CXL* R-Tile
  • Up to PCIe* 5.0 ×16 EP
  • Selected features support CXL 1.1 and 2.0 specifications
  • Soft logic to support Type 1, Type 2, or Type 3 devices
  • Mix and manage different memory types and controllers
Other protocols E-Tile
  • Ethernet IP configurations:
    • 24× 10 or 25 GbE MAC, PCS, and RS-FEC
    • 4× 100 GbE MAC, PCS, and RS-FEC
  • CPRI and fibre channel FECs
  • CR/KR (AN/LT)
  • 1588 PTP
  • MAC, PCS, and FEC bypass options
  • PMA Direct Mode
F-Tile
  • Ethernet IP Configurations:
    • 16× 10 or 25 GbE MAC, PCS, and FEC
    • 8× 50 GbE MAC, PCS, and FEC
    • 8× 40 GbE MAC, PCS, and FEC
    • 4× 100 GbE MAC, PCS, and FEC
    • 1× 400 GbE MAC, PCS, and FEC
  • KP FEC support
  • Flex-O FEC, FlexE PCS and FEC, Ethernet over OTN Mode, SyncE, fibre channel, and CPRI FEC
  • CR/KR (AN/LT)
  • 1588 PTP
  • MAC, PCS, and FEC bypass options
  • PMA Direct Mode
D-Series
  • Ethernet IP configuration: 16× 10 or 25 GbE MAC, PCS, and FEC
  • CPRI and fibre channel
  • CR/KR (AN/LT)
  • 1588 PTP
  • MAC, PCS, and FEC bypass options
Configuration
  • Dedicated SDM
  • Software-programmable device configuration
  • Fine-grained partial reconfiguration of core fabric—add or remove system logic while the device is operating
  • Dynamic reconfiguration of transceivers and PLLs
  • PUF service
  • Platform attestation
  • Anti-tamper features
F-Series
  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCIe* 1.0, 2.0, 3.0, or 4.0
  • Comprehensive set of security features including AES-256, SHA-256/384, ECDSA-256/384 accelerators, and multi-factor authentication

I-Series

M-Series

  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCIe* 1.0, 2.0, 3.0, 4.0, or 5.0
  • Comprehensive set of security features including AES-256, SHA-256/384, ECDSA-256/384 accelerators, and multi-factor authentication
D-Series
  • Serial flash interface
  • Configuration via protocol (CvP) using PCIe* 1.0, 2.0, 3.0, or 4.0
  • Configuration from parallel flash through external host
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators
Software and tools
  • Intel® Quartus® Prime Pro Edition design suite with new compiler and Hyper-Aware design flow
  • New compile innovations in each Intel® oneAPI release
  • Transceiver toolkit
  • Platform Designer IP integration tool
  • Intel® DSP Builder for Intel® FPGAs advanced blockset
  • Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA)
7 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
8 Only available in select devices. Refer to the family plan.

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