Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

2.1. Intel® Agilex™ F-Series FPGAs and SoCs

Table 4.   Intel® Agilex™ F-Series Device Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device

Logic Element

Adaptive Logic Module eSRAM M20K

MLAB

DSP Crypto Block
Count Size (Mb) Count

Size (Mb)

Count Size (Mb) Count 18×19 Multiplier
AGF 006 573,480 194,400 2,844 56 9,720 6 1,640 3,280
AGF 008 764,640 259,200 3,792 74 12,960 8 2,296 4,592
AGF 012 1,178,525 399,500 2 36 5,900 115 19,975 12 3,743 7,486
AGF 014 1,437,240 487,200 2 36 7,110 139 24,360 15 4,510 9,020
AGF 019 1,918,975 650,500 1 18 8,500 166 35,525 20 1,354 2,708 2
AGF 023 2,308,080 782,400 1 18 10,464 204 39,120 24 1,640 3,280 2
AGF 022 2,208,075 748,500 10,900 212 37,425 23 6,250 12,500
AGF 027 2,692,760 912,800 13,272 259 45,640 28 8,528 17,056
Table 5.   Intel® Agilex™ F-Series Device Family Plan—Transceivers and HPS

The values in this table are maximum resources or performance.

Device F-Tile P-Tile E-Tile

HPS Option

FGT Transceiver Channel 9

Ethernet Block

10

PCIe* Controller

11

PCIe* Controller

11

Transceiver

Channel 12

Ethernet Block

13

32 Gbps

NRZ

58 Gbps

PAM4

28.9 Gbps

NRZ

58 Gbps

PAM4

AGF 006 32

24

2 2 Yes
AGF 008 32

24

2 2 Yes
AGF 012 32

24

2 2 1 16

8

4 Yes
AGF 014 32

24

2 2 1 16

8

4 Yes
AGF 019 64

48

4 4 2 24

12

4 Yes
AGF 023 64

48

4 4 2 24

12

4 Yes
AGF 022 64

48

4 4 2 24

12

4 Yes
AGF 027 64

48

4 4 2 24

12

4 Yes
Table 6.   Intel® Agilex™ F-Series Packages with F-TileTable reading example: In package 1546A of AGF 006, there are 384 GPIOs, of which, 192 are LVDS. There are two F-Tilessupporting a maximum total of 32× 32 Gbps NRZ or 24× 58 Gbps PAM4.
Device Package

(Grid Array: Hexagonal)

1546A

(37.5 mm × 34 mm)

0.92 mm pitch

2340A

(45 mm × 42 mm)

0.92 mm pitch

3184C

(56 mm × 45 mm)

0.92 mm pitch

GPIO LVDS F-Tile ×2 GPIO LVDS F-Tile ×2 GPIO LVDS F-Tile ×4
32 Gbps

NRZ

58 Gbps

PAM4

32 Gbps

NRZ

58 Gbps

PAM4

32 Gbps

NRZ

58 Gbps

PAM4

AGF 006 384 192 32 24 576 288 32 24
AGF 008 384 192 32 24 576 288 32 24
AGF 012 744 372 32 24
AGF 014 744 372 32 24
AGF 019 480 240 32 24 480 240 64 48
AGF 023 480 240 32 24 480 240 64 48
AGF 022 744 372 32 24 720 360 64 48
AGF 027 744 372 32 24 720 360 64 48
Table 7.   Intel® Agilex™ F-Series Packages with P-Tile and E-TileTable reading example: In package 2581A of AGF 019, there are 480 GPIOs, of which, 240 are LVDS. There is one E-Tile supporting a maximum of 24× 28.9 Gbps NRZ or 12× 58 Gbps PAM4. There are two P-Tiles supporting a maximum total of 32× PCIe* at up to 16 Gbps per lane.
Device Package

(Grid Array: Hexagonal)

2486A

(55 mm × 42.5 mm)

1.0 mm pitch

2581A

(52.5 mm × 40.5 mm)

0.92 mm or 0.94 mm pitch

GPIO LVDS E-Tile ×1 P-Tile ×1 GPIO LVDS E-Tile ×1 P-Tile ×2
28.9 Gbps

NRZ

58 Gbps

PAM4

16 Gbps

PCIe*

28.9 Gbps

NRZ

58 Gbps

PAM4

16 Gbps

PCIe*

AGF 006
AGF 008
AGF 012 768 384 16 8 16
AGF 014 768 384 16 8 16
AGF 019 480 240 24 12 32
AGF 023 480 240 24 12 32
AGF 022 624 312 24 12 32
AGF 027 624 312 24 12 32
9 Maximum F-Tile general purpose transceiver (FGT) RS and KP FEC NRZ up to 32 Gbps, or PAM4 up to 58 Gbps.
10 Maximum 10, 25, 40, 50, 100, 200, or 400 GbE MAC and FEC hard IP blocks.
11 Maximum PCIe* hard IP blocks ( PCIe* 4.0 ×16) or bifurcatable two PCIe* 4.0 ×8 (EP) or four PCIe* 4.0 ×4 (RP).
12 Maximum RS and KP FEC NRZ up to 28.9 Gbps, or PAM4 up to 58 Gbps.
13 Maximum 100 GbE MAC and FEC hard IP blocks

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