7. Core Clock Network in Intel® Agilex™ 7 FPGAs and SoCs
Programmable clock tree synthesis uses dedicated clock tree routing and switching circuits. These dedicated circuits enable the Intel® Quartus® Prime software to create the exact clock trees that your design requires.
Advantages of using programmable clock tree synthesis:
- Minimizes clock tree insertion delay
- Reduces dynamic power dissipation in the clock tree
- Allows greater flexibility of clocking in the core
- Maintains backwards compatibility with legacy global and regional clocking schemes
Features of the core clock network of Intel® Agilex™ 7 FPGAs and SoCs:
- Supports the second generation Intel® Hyperflex™ core architecture
- Supports the hard memory controllers31 for:
- DDR4—up to 3,200 Mbps with a quarter-rate transfer to the core
- DDR5—up to 5,600 Mbps
- LPDDR5—up to 5,500 Mbps
- Supported by dedicated clock input pins and integer I/O PLLs
Did you find the information on this page useful?