1.1.4. Common Features
- On-chip multi-level memory hierarchy blocks including MLAB (640 b), M20K (20 Kb), and eSRAM (18 Mb—not available in Intel® Agilex™ M-Series devices)
- Variable precision DSP blocks with hard IEEE 754 compliant floating-point units, including support for single-precision FP32 (32-bit arithmetic), half-precision FP16 (16-bit arithmetic) floating point modes and BFLOAT16 floating-point format.
- Integer PLLs
- Hard memory controllers and PHY for external memory interfaces
- General purpose I/O cells
To clock these building blocks, Intel® Agilex™ FPGA devices employ programmable clock tree synthesis using a dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while under operation.
All family variants’ high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols such as 10/25/100 GE MAC, PCS, FEC in E-tiles, and 10/25/40/50/100/200/400 GE MAC, PCS, FEC in F-tiles.
In addition to the hard PCS, Intel® Agilex™ FPGAs devices contain multiple instantiations of PCI Express* hard IP that supports Gen1/Gen2/Gen3/Gen4/Gen5 rates in x1/x2/x4/x8/x16 lane configurations (Gen5 in Intel® Agilex™ I-series and M-series devices). The hard PCS, and PCI Express* IP free up valuable core logic resources, save power and increase your productivity.
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