Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.1.4. Common Features

Common to all Intel® Agilex™ FPGAs family variants is a high-performance fabric based on the second generation Intel® Hyperflex™ core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:
  • On-chip multi-level memory hierarchy blocks including MLAB (640 b), M20K (20 Kb), and eSRAM (18 Mb—not available in Intel® Agilex™ M-Series devices)
  • Variable precision DSP blocks with hard IEEE 754 compliant floating-point units, including support for single-precision FP32 (32-bit arithmetic), half-precision FP16 (16-bit arithmetic) floating point modes and BFLOAT16 floating-point format.
  • Integer PLLs
  • Hard memory controllers and PHY for external memory interfaces
  • General purpose I/O cells

To clock these building blocks, Intel® Agilex™ FPGA devices employ programmable clock tree synthesis using a dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while under operation.

All family variants’ high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols such as 10/25/100 GE MAC, PCS, FEC in E-tiles, and 10/25/40/50/100/200/400 GE MAC, PCS, FEC in F-tiles.

In addition to the hard PCS, Intel® Agilex™ FPGAs devices contain multiple instantiations of PCI Express* hard IP that supports Gen1/Gen2/Gen3/Gen4/Gen5 rates in x1/x2/x4/x8/x16 lane configurations (Gen5 in Intel® Agilex™ I-series and M-series devices). The hard PCS, and PCI Express* IP free up valuable core logic resources, save power and increase your productivity.

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