Intel® Agilex™ FPGAs and SoCs Device Overview

ID 683458
Date 9/26/2022
Public
Document Table of Contents
1. Overview of the Intel® Agilex™ FPGAs and SoCs 2. Intel® Agilex™ FPGAs and SoCs Family Plan 3. Second Generation Intel® Hyperflex™ Core Architecture 4. Adaptive Logic Module in Intel® Agilex™ FPGAs and SoCs 5. Internal Embedded Memory in Intel® Agilex™ FPGAs and SoCs 6. Variable-Precision DSP in Intel® Agilex™ FPGAs and SoCs 7. Core Clock Network in Intel® Agilex™ FPGAs and SoCs 8. General Purpose I/Os in Intel® Agilex™ FPGAs and SoCs 9. I/O PLLs in Intel® Agilex™ FPGAs and SoCs 10. External Memory Interface in Intel® Agilex™ FPGAs and SoCs 11. Hard Processor System in Intel® Agilex™ SoCs 12. FPGA Transceivers in Intel® Agilex™ FPGAs and SoCs 13. Heterogeneous 3D Stacked HBM2E DRAM Memory in Intel® Agilex™ M-Series FPGAs and SoCs 14. High-Performance Crypto Blocks in Intel® Agilex™ F-Series and I-Series FPGAs and SoCs 15. MIPI* Protocols Support in Intel® Agilex™ D-Series FPGAs and SoCs 16. Balls Anywhere Package Design of Intel® Agilex™ D-Series FPGAs and SoCs 17. Configuration via Protocol Using PCIe* for Intel® Agilex™ FPGAs and SoCs 18. Device Configuration and the SDM in Intel® Agilex™ FPGAs and SoCs 19. Partial and Dynamic Configuration of Intel® Agilex™ FPGAs and SoCs 20. Device Security for Intel® Agilex™ FPGAs and SoCs 21. SEU Error Detection and Correction in Intel® Agilex™ FPGAs and SoCs 22. Power Management for Intel® Agilex™ FPGAs and SoCs 23. Intel® Software and Tools for Intel® Agilex™ FPGAs and SoCs 24. Revision History for the Intel® Agilex™ FPGAs and SoCs Device Overview

1.10. Adaptive Logic Module (ALM)

Intel® Agilex™ devices use an enhanced adaptive logic module (ALM) similar to the previous generation Intel® Stratix® 10 and Intel® Arria® 10 FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with fracturable look-up table (LUT), two dedicated embedded adders and four dedicated registers.

Figure 8. ALM Block Diagram

Key features and capabilities of the ALM include:

  • High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the second generation Intel® Hyperflex™ architecture enables Intel® Agilex™ devices to maximize core performance at very high core logic utilization
  • Implements select 7-input logic functions, all 6-input logic functions and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization
  • New in Intel® Agilex™ ALM architecture are two clock sources for each ALM which generate two normal clocks and two delayed clocks to drive the ALM registers; resulting in more clock domains and time-borrowing capability
  • Additional fast 6 LUT and 5 LUT outputs for combinatorial functions; resulting in improved critical path for cascade of logic
  • Improved register packing mode, including 5-input LUT with 2 packed register paths resulting in more efficient usage of the fabric area leading to improved critical path
  • New support for latch mode in the address latch enable

The Intel® Quartus® Prime software capitalize on the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel® Quartus® Prime software simplifies design reuse as it automatically maps legacy designs into the Intel® Agilex™ FPGA’s ALM architecture.

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