Agilex™ 7 Power Management User Guide

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ID 683373
Date 11/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Power Management Overview 2. Agilex™ 7 Power Basics 3. Agilex™ 7 Power and I/O State Sequencing 4. Agilex™ 7 Sensor Monitoring System 5. Agilex™ 7 Power Optimization Techniques and Features 6. Document Revision History for the Agilex™ 7 Power Management User Guide
1. Agilex™ 7 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 7 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 7 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Power-Down Sequence Requirements for Agilex™ 7 Devices with E-Tile 3.4. Power-Down Sequence Requirements for the Agilex™ 7 M-Series Devices 3.5. Floating Voltage 3.6. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in GPIO, HPS, SDM Banks, and UIB Subsystem During Power Sequencing
3.6. Power-On Reset x
3.6.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 7 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations 4.4. Temperature Reading Design Example
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.2.3. Temperature Sensor Locations x
4.2.3.1. Getting Approximate Locations of the Transceiver Banks
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Temperature Monitor Design Guidelines 4.3.3. Transceiver Tile Local Temperature Sensor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 7 Remote TSD 4.3.5. Guidelines: Reading the R-Tile Local Temperature Sensor
4.4. Temperature Reading Design Example x
4.4.1. Directory Structure 4.4.2. Hardware and Software Requirements 4.4.3. Temperature Reading Design Example Description 4.4.4. Using the Temperature Reading Design Example 4.4.5. Verifying the Interaction between the Design Example and the Mailbox Client with Avalon® Streaming Interface IP
4.4.4. Using the Temperature Reading Design Example x
4.4.4.1. Opening the Temperature Reading Design Example 4.4.4.2. Compiling the Temperature Reading Design Example and Generating the Software Object File 4.4.4.3. Programming and Starting Up the Temperature Reading Design Example 4.4.4.4. Sending Commands to the Temperature Reading Design Example
4.4.4.4. Sending Commands to the Temperature Reading Design Example x
4.4.4.4.1. Default Commands for the Temperature Reading Design Example
5. Agilex™ 7 Power Optimization Techniques and Features x
5.1. SmartVID Standard Power Devices 5.2. DSP and M20K Power Gating 5.3. Clock Gating 5.4. Power Sense Line 5.5. Power Optimization Techniques in the Quartus® Prime Software
5.1. SmartVID Standard Power Devices x
5.1.1. SmartVID Feature Implementation in Agilex™ 7 Devices 5.1.2. SDM Power Manager 5.1.3. Temperature Compensation 5.1.4. Agilex™ 7 Power Management and VID Implementation Guide
5.1.2. SDM Power Manager x
5.1.2.1. PMBus Master Mode 5.1.2.2. PMBus Slave Mode 5.1.2.3. Fail Safe Mechanism 5.1.2.4. Fault Management and Error Reporting
5.1.4. Agilex™ 7 Power Management and VID Implementation Guide x
5.1.4.1. Specifying Power Management and VID Parameters and Options
5.1.4.1. Specifying Power Management and VID Parameters and Options x
5.1.4.1.1. Configuration Pin Parameters 5.1.4.1.2. Power Management and VID Parameters 5.1.4.1.3. Power Management and VID Interface QSF Constraint Guide
1. Agilex™ 7 Power Management Overview
2. Agilex™ 7 Power Basics
3. Agilex™ 7 Power and I/O State Sequencing
4. Agilex™ 7 Sensor Monitoring System
5. Agilex™ 7 Power Optimization Techniques and Features
6. Document Revision History for the Agilex™ 7 Power Management User Guide

6. Document Revision History for the Intel® Agilex™ Power Management User Guide

Document Version Changes
2022.12.19
  • Added the Floating Voltage section.
  • Updated the document title from Intel® Agilex™ Power Management User Guide to Intel® Agilex™ F-Series and I-Series Power Management User Guide.
  • Updated the VID-fused value in the SmartVID Feature Implementation in Intel® Agilex™ Devices section.
  • Updated the PMBus Master Mode section.
  • Updated the default value of the VOUT_MODE command and the PMBus transaction type of the CLEAR_FAULTS command in Table: Supported Commands for the PMBus Master Mode.
2022.09.06 Updated the Multi-Master Mode section.
2022.08.08 Updated the F-tile and R-tile bank names for location 7 in the table listing the local temperature sensor locations and corresponding transceiver bank names.
2022.06.21
  • Updated the topic about the temperature sensor locations:
    • Updated the list of devices for each location diagram.
    • Added a table listing the local temperature sensor locations and corresponding transceiver bank names.
  • Updated Table: Voltage Rails Group.
  • Updated Figure: Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode.
2022.05.27 Removed instances of Enpirion from Choosing a Power Tree and Power Generation sections and Power Management and VID Parameters table.
2022.04.15
  • Updated the Power-Up Sequence Requirements section to include details for the VCCBAT power supply.
  • Removed the VCCBAT power supply from the Power Supplies Monitored by the POR Circuitry section.
2022.04.04
  • Added the Fail Safe Mechanism section.
  • Added the Fault Management and Error Reporting section.
  • Added Figure: Flow between the PMBus Voltage Regulator and FPGA in the PMBus Master Mode.
  • Updated the Clock Gating section.
  • Updated the Intel® Agilex™ Power Management and VID Interface QSF Constraint Guide section.
  • Updated Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT.
  • Updated the VCCH_FGT_GXF and VCCEHT_FHT_GXF power rails in Table: Voltage Rails Group .
  • Updated Table: Power Management and VID Parameters to include ISL682XX voltage regulator.
  • Updated the descriptions of the figures showing the temperature sensing diode locations to clarify that each figure shows the top view of the die. In the Intel® Quartus® Prime Chip Planner, the view is flipped.
2022.01.25 Updated the topic that shows the temperature sensor locations to clarify that the figures show the top view of the devices as shown in the Intel® Quartus® Prime Chip Planner.
2021.12.13 Updated the VCCRCORE pin name.
2021.10.29
  • Added Table: Power Rails Status for Intel® Agilex™ Devices.
  • Added Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE=0.
  • Added Table: Stage Flow for the External PMBus Master without the PWRMGT_ALERT Signal and STATUS_BYTE is not Equal to 0.
  • Added Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode with PWRMGT_ALERT .
  • Added Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram without the PWRMGT_ALERT Signal.
  • Added Figure: Handshake Flow between the External PMBus Master and FPGA in the PMBus Slave Mode without PWRMGT_ALERT .
  • Updated Table: Comparison of Intel® FPGA Power and Thermal Calculator and Intel® Quartus® Prime Power Analyzer Capabilities.
  • Updated Table: Supported Commands for the PMBus Master Mode.
  • Updated Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE=0.
  • Updated Table: Stage Flow for the External PMBus Master when the PWRMGT_ALERT Signal is Asserted and STATUS_BYTE is not equals to 0.
  • Updated Table: Configuration Pin Parameters.
  • Updated Table: Power Management and VID Parameters.
  • Updated Table: Local Temperature Sensor Locations and Equivalent Remote TSD Pin Names.
  • Updated Figure: PMBus Slave Mode.
  • Updated Figure: Temperature Sensing Diode Locations— Intel® Agilex™ AGF 006 and AGF 008.
  • Updated Figure: Temperature Sensing Diode Locations— Intel® Agilex™ AGF 012, AGF 014, AGF019, AGF 022, AGF023, AGF 027, AGI019, AGI 022, AGI023, and AGI 027.
  • Updated the Intel® Agilex™ Power Management Overview section.
  • Updated the Catastrophic Trip Signal section.
  • Updated the Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing section.
  • Updated the Power-Down Sequence Requirements for Intel® Agilex™ Devices with E-Tile section.
  • Updated the SmartVID Standard Power Devices section.
  • Updated the PMBus Master Mode section.
  • Updated the PMBus Slave Mode section.
  • Updated the Specifying Power Management and VID Parameters and Options section.
  • Removed the Intel® Agilex™ Power Management and VID Interface Getting Started section and merged the content into the Intel® Agilex™ Power Management and VID Implementation Guide section.
  • Removed Figure: External PMBus Master Software Flow.
2021.07.02
  • Updated the SmartVID Standard Power Devices section.
  • Updated the SmartVID Feature Implementation in Intel® Agilex™ Devices section.
  • Updated the SDM Power Manager section.
  • Updated the Temperature Compensation section.
  • Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
  • Updated Figure: Temperature Compensation for SmartVID for Intel® Agilex™ Devices.
2021.06.09
  • Updated the catastrophic trip signal information. The signal now drives low when the temperature is higher than 120°C.
2021.04.13
  • Added information for temperature sensors in R-tile and F-tile transceivers.
  • Added the Multi-Master Mode section.
  • Added reference to the Intel® Stratix® 10 and Intel® Agilex™ SmartVID Debug Checklist.
  • Added reference to the Intel® FPGA Power and Thermal Calculator Standalone and Intel® FPGA Power and Thermal Calculator User Guide.
  • Updated the Intel® FPGA Power and Thermal Calculator .
  • Updated the SmartVID Standard Power Devices section to include the –X power option.
  • Updated Table: Supported Voltage Output Format for Intel Agilex Devices with the –V, –E, and –X Power Options.
  • Updated the description of the slave device type and voltage output format parameters in Table: Power Management and VID Parameters.
  • Updated Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
  • Updated Figure: External PMBus Master Software Flow.
  • Removed VCCBAT from Table: Voltage Rails Group.
  • Removed the H-tile support.
2021.02.08
  • Updated the topic about the voltage monitoring system to clarify about internal high-voltage rails.
  • Added VCCR_CORE (channel 5) to the figure showing the Intel® Agilex™ voltage sensor.
  • Corrected the TSD location numbers for reading the temperatures of the HPS and SDM blocks.
  • Updated the footnotes to the table that lists the local temperature sensor locations to clarify that channel 0 returns the highest temperature in a location for any location that has more than one TSD.
  • Added the temperature sensor error codes.
  • Added the Temperature Reading design example section.
2020.11.11 Updated the footnote for VCCA_PLL and VCCR_CORE in Table: Voltage Rails Group.
2020.10.19
  • Updated the SmartVID value and SmartVID programmed value terms to VID-fused value.
  • Added the Power-Down Sequence Requirements for Intel® Agilex™ Devices with E-Tile or H-Tile section.
  • Updated the Power-Up Sequence Requirements section to include details about the power-down sequence for E-tile and H-tile devices.
  • Updated the SDM Power Manager section.
  • Updated the PMBus Slave Mode section.
  • Updated the Temperature Compensation section.
  • Updated Table: Voltage Rails Group.
  • Updated Table: Power Management and VID Parameters to update the description of the Slave device type and Enable PAGE command parameters.
  • Added Figure: Handshake between the External PMBus Master and FPGA in the PMBus Slave Mode Timing Diagram.
  • Added Figure: Power-Down Sequence for Intel® Agilex™ Devices with H-Tile.
  • Added Figure: Power-Down Sequence for Intel® Agilex™ Devices with E-Tile.
  • Updated Figure: Temperature Compensation for SmartVID for Intel® Agilex™ Devices.
  • Removed note (2) from Figure: External PMBus Master Software Flow.
  • Updated Example 1—Specifying the Power Management and VID Parameters through QSF Constraints.
  • Updated the voltage monitor range to up to 1.10 V.
  • Updated the figure showing the voltage monitor 7-bit unipolar transfer function.
  • Updated the table that provides an overview of the local and remote temperature sensors.
  • Updated the topic about the local temperature sensors.
  • Updated the figures showing the TSD locations.
  • Updated the table listing the temperature sensor locations, channels, and remote TSD pin names.
  • Updated the topic about retrieving the local temperature sensor reading.
  • Added guidelines topic about calibrating the external temperature sensing chip.
  • Renamed "Mailbox Avalon® ST Client Intel® FPGA IP" to "Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP".
2020.04.22
  • Added the Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing section.
  • Added the F-tile and R-tile power rails in the Voltage Rails Group table.
  • Added VCCR_CORE power supply to the Power Supplies Monitored by the POR Circuitry section.
  • Added the Supported Voltage Output Format for Intel® Agilex™ Devices with the –V and –E Power Options table.
  • Updated the table that provides an overview of the local and remote temperature sensors to clarify that the local temperature sensor operates only in user mode.
  • Updated the topic about the temperature sensor channels and locations:
    • Updated the description from using "channels" to "locations".
    • Updated the diagram showing the sensor locations.
    • Updated the table listing the sensor locations and equivalent remote TSD pins.
  • Added topic about retrieving the local temperature sensor reading.
  • Updated the voltage monitor design guidelines to add VSIGP and VSIGN pins guideline.
  • Added the E-tile transceiver local temperature sensor design guidelines.
2020.02.06
  • Updated the PMBus Slave Mode section.
  • Added VCC_HSSI_GXE , VCCRTPLL_GXE , VCCR_CORE , VCCIO_PIO_SDM , and VCCBAT power rails to the Voltage Rails Group table.
  • Removed VCCRTPLL_CR3_GXE and VCCM_WORD power rails from the Voltage Rails Group table.
  • Removed the Power Distribution section.
2019.10.04
  • Changed the Early Power Estimator (EPE) tool name to Intel® FPGA Power and Thermal Calculator.
  • Added the Intel® Agilex™ Power Management and VID Interface QSF Constraint Guide section.
  • Added ED8401, EM21XX, and EM22XX device selection in the slave device type parameters in the Power Management and VID Parameters table.
  • Updated the power optimization information in the Intel® Agilex™ Power Management Overview section.
  • Updated the Early Power Estimator (EPE) section.
  • Updated the Power Supplies Monitored by the POR Circuitry section to remove the note on powering up VCCBAT when not using the volatile key.
  • Updated the SmartVID Standard Power Devices section to update the voltage value for VCC and VCCP during power up.
  • Updated the VCCA_PLL power rail from Group 2 to Group 3 in the Voltage Rails Group table.
  • Updated the Stage Flow for the External Power Management Controller in the PMBus Slave Mode figure.
  • Changed the voltage and temperature sensors IP support from Temperature Sensor and Voltage Sensor IPs to Mailbox Client and Mailbox Avalon® ST IPs.
  • Updated the Local Temperature Sensor topic to add information about the catastrophic trip (nCATTRIP) signal.
  • Added reference to the Intel® Agilex™ Design Guideline Training: IBIS AMI Link Simulation, PDN, EMIF Layout Guidelines.
  • Removed the Power Dissipation and Thermal Considerations section.
2019.04.02 Initial release.
Level Two Title