DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023
Public

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15.3.25. Twiddle and Variable Twiddle (Twiddle and VTwiddle)

The Twiddle and VTwiddle blocks are low-level blocks that implement streaming FFTs.

Each twiddle block joins two FFTs (the left constituent FFT and the right constituent FFT) to form a larger FFT. For variable-size FFTs, use the VTwiddle block. Each of the constituent FFTs is either a primitive FFT (e.g. an FFT4 block) or is multiple FFT and twiddle blocks.

The Twiddle block FFT may be part of an even larger FFT. In fact, the pipeline is formed by linearizing a binary tree of FFTs (leaf nodes) and twiddle blocks (internal nodes).

Each Twiddle block requires you to specify three types:

  • The data signal prior to the twiddle multiplications
  • The twiddle factors
  • The data signal after the twiddle multiplication.
    Table 147.  Parameters for the Twiddle and VTwiddle Block
    Parameter Description
    iFFT Generate twiddle factors for an FFT or an IFFT.
    Stages before this The number of stages to the left(*) of this composite FFT.
    Left width The number of stages in the left(*) constituent FFT.
    Right width The number of stages in the right(*) constituent FFT.
    Stages after this The number of stages to the right(*) of this composite FFT.
    Input type The type to which DSP Builder should convert the input. Refers to the type of the input after you apply an explicit type conversion. It doesn't have to exactly match the actual input type to the Twiddle block.
    Twiddle type The type of the twiddle factor.
    Output type The type of the output after the twiddle.
    Use faithful rounding Use faithful rather than correct rounding. Fixed-point FFTs ignore this parameter.
Note: For bit-reversed FFTs, reverse left and right, so left refers to the number of stages to the right of the current block.
Table 148.  Port Interface for the Twiddle and VTwiddle Blocks
Signal Direction Type Description
v Input Boolean Valid input signal.
d Input Any complex type Complex data input signal.
drop Input uint(k) for some k Total number of FFT stages to bypass
qv Output Boolean Valid output signal.
q Output Any complex type Complex data output signal.
qdrop Output uint(k) for some k Total number of FFT stages to bypass