7. DSP Builder for Intel FPGAs (Advanced Blockset) Design Examples and Reference Designs
All the design examples have the same basic structure: a top-level testbench containing an instantiated functional subsystem, which represents the hardware design.
The testbench typically includes Simulink source blocks that generate the stimulus signals and sink blocks that display simulation results. You can use other Simulink blocks to define the testbench logic.
The testbench also includes the following blocks from the DSP Builder advanced blockset:
- The Control block specifies information about the hardware generation environment, and the top-level memory-mapped bus interface widths.
- The ChanView block in a testbench allows you to visualize the contents of the <valid, channel, data> time-division multiplex (TDM) protocol. This block generates synthesizable HDL and can therefore also be useful in a functional subsystem.
The functional subsystem in each design contains a Device block that marks the top-level of the FPGA device and controls the target device for the hardware.