You can hierarchically separate parts of the design into synthesizeable systems. You must use a Device block, which sets the device family, part number, speed grade, and so on, to indicate the top-level synthesizable system.
You can further hierarchically split the synthesizeable system into Primitive subsystems for Primitive blocks and IP blocks.
You can optionally include LocalThreshold blocks to override threshold settings defined higher up the hierarchy.
DSP Builder generates project files and scripts that relate to this level of hierarchy. All blocks in subsystems below this level become part of the RTL design. All blocks above this level of hierarchy become part of the testbench.
You can insert multiple Device blocks in non-overlapping subsystems to use multiple FPGAs in the same design. You can mix device families freely.
|Device family||Select the required target device family.|
|Device||Select the specific device.|
|Family member||Specify the device member as free-form text or enter AUTO for automatic selection.|
|Speed grade||Select the speed grade for the FPGA target device.|