126.96.36.199. Common CIC and FIR Filter Features
- Filter length from 1 to unlimited taps
- Data input width from 2 to 32 bits
- Data output width from 4 to 64 bits
- Multichannel (up to 256 channels)
- Powerful MATLAB integration
- Simulink fixed-point integration
- Automatic pipelining
- Plug and play connectivity
- Simplified timing closure
- Generates updated help for your parameters
The required system clock frequency, and the device family and speed grade determine the maximum logic depth permitted in the output RTL. DSP Builder pipelines functions such as adders by splitting them into multiple sections with a registered carry between them. This pipelining decreases the logic depth allowing higher frequency operation.
The DSP Builder filter generator is responsive to the system clock frequency, therefore timing closure is much easier to achieve. The generator uses heuristics that ensure the logic can run at the desired system clock frequency on the FPGA. You can help timing closure by adding more clock margin, resulting in additional pipelining that shortens the critical paths.The FPGA structures such as internal multiplier and memory delays determine the maximum clock frequencies.
In some cases, the aggregate sample rate for all channels may be higher than the system clock rate. In these cases, the filter has multiple input or output buses to carry the additional data, so DSP Builder implements this requirement in the Simulink block by increasing the vector width of the data signals.
You can generate filter coefficients using a MATLAB function that reloads at run time with the memory-mapped interface registers. For example, the Simulink fixed-point object fi(fir1(49, 0.3),1,18,19)
The generated help page for the block shows the input channel data format and output data channel format that a FIR or CIC filter uses, after you run a Simulink simulation.