DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023
Public

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Document Table of Contents

6.3. Viewing Timing Closure and Viewing Resource Utilization for the DSP Builder IP Design

Compile the IP design in the Quartus Prime software

Procedure

  1. View timing closure:
    1. In the Task pane, expand Timing Analyzer.
    2. Double-click View Report.
    3. In the Table of Contents pane expand Slow 900mV 85C Model and click Fmax Summary.
  2. View the resource utilization:
    1. On the Task pane expand Fitter (Place & Route).
    2. Double-click View Report.
    3. In the Table of Contents pane expand Resource Section and click Resource Usage Summary, which shows the number of DSP block 18-bit elements.