DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/01/2023

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7.6.2. Position, Speed, and Current Control for AC Motors (with ALU Folding)

The position, speed, and current control for AC motors (with ALU folding) design example is a FOC algorithm for AC motors, which is identical to the position, speed, and current control for AC motors design example. However this design example uses ALU folding.

The model file is psc_ctrl_alu.mdl.

The design example targets a Cyclone V device (speed grade 8). Cyclone V devices have distributed memory (MLABs). ALU folding uses many distributed memory components. ALU folding performs better in devices that have distributed memories, rather than devices with larger block memories.

The design example includes a setup script setup_position_speed_current_controller_alu.m.

Table 16.  Setup Script Variables
Variables Description
dspb_psc_ctrl.SampleRateHz = 10000 Sample rate. Default set to 10000, which is 10 kHz sample rate.
dspb_psc_ctrl.ClockRate = 100 FPGA clock frequency. Default set to 100, which is 100 MHz clock
dspb_psc_ctrl.LatencyConstraint = 1000 Maximum latency. Default 1,000 clock cycles

This design example uses a significantly large maximum latency, so resource consumption is the factor to optimize in ALU folding rather than latency.

Generally, industrial designs require a testbench that operates at the real-world sample rate. This example emulates the behavior of a motor sending current, position, and speed samples at a rate of 10 kHz.

When you run this design example without folding, the DSP Builder system operates at the same 10 kHz sample rate. Therefore, the system calculates a new packet of data for every Simulink sample. Also, the sample times of the testbench are the same as the sample times for the DSP Builder system.

The Rate Transition blocks translate between the Simulink testbench and the DSP Builder system. These blocks allow Simulink to manage the different sample times that the DSP Builder system requires. You need not modify the design example when you run designs with or without folding.

The Rate Transition blocks produce Simulink samples with a sample time of dspb_psc_ctrl.SampleTime for the testbench and dspb_psc_ctrl.DSPBASampleTime for the DSP Builder system. The samples are in the stimuli system, within the dummy motor. To hold the data consistent at the inputs to the Rate Transition blocks for the entire length of the output sample (dspb_psc_ctrl.SampleTime), turn on Register Outputs.

The data valid signal consists of a one Simulink sample pulse that signifies the beginning of a data packet followed by zero values until the next data sample, as required by ALU folding. The design example sets the period of this pulsing data valid signal to the number of Simulink samples for the DSP Builder system (at dspb_psc_ctrl.DSPBASampleTime) between data packets. This value is dspb_psc_ctrl.SampleTime/dspb_psc_ctrl.DSPBASampleTime.

The verification script within ALU folding uses the To Workspace blocks. The verification script searches for To Workspace blocks on the output of systems to fold. The script uses these blocks to record the outputs from both the design example with and without folding. The script compares the results with respect to valid outputs. To run the verification script, enter the following command at the MATLAB prompt: