9.5.1. Managing Basic Parameters
Based on the FPGA clock rate and data sample rates, you can derive how many clock cycles are available to process unique data samples. This parameter is called Period in many of the design examples. For example, for a period of three, a new sample for the same channel appears every three clock cycles. For multiplication, you have three clock cycles to compute one multiplication for this channel. In a design with multiple channels, you can accommodate three different channels with just one multiplier. A resource reuse potential exists when the period is greater than one.
- FPGA clock rate
- Data sample rates at various stages of your design
- Number of channels or data sources
- Bit widths of signals at various stages of your design, including possible bit growth throughout the computational datapath
- Coefficients of filters